CXL interconnect specification

By: Robert Williams (crispysilicon.delete@this.gmail.com), March 11, 2019 10:40 am
Room: Moderated Discussions
https://www.anandtech.com/show/14068/cxl-specification-1-released-new-industry-high-speed-interconnect-from-intel

It uses existing PCIe physically and electrically. It's also coherent.

I'm heading to Intel's new GPU showcase on the 20th, wonder if their showcase hardware is running this?
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TopicPosted ByDate
CXL interconnect specificationRobert Williams2019/03/11 10:40 AM
  CXL interconnect specificationJeff S.2019/03/11 11:17 AM
  CXL interconnect specificationraider19822019/03/11 02:06 PM
    CXL interconnect specificationraider19822019/03/11 02:06 PM
    CXL interconnect specificationRobert Williams2019/03/11 03:40 PM
      CXL interconnect specificationdmcq2019/03/12 02:10 AM
      CXL interconnect specificationMaynard Handley2019/03/12 06:14 AM
        CXL interconnect specificationJeff S.2019/03/12 06:29 AM
          CXL interconnect specificationMontaray Jack2019/03/13 03:43 PM
  CXL interconnect specificationMichael_S2019/03/11 02:10 PM
    CXL interconnect specificationLinus Torvalds2019/03/11 02:38 PM
      CXL interconnect specificationdmcq2019/03/11 05:34 PM
      CXL interconnect specificationRobert Williams2019/03/13 08:57 AM
    CXL interconnect specificationAaron Spink2019/03/11 09:07 PM
      CXL interconnect specificationMichael S2019/03/12 01:49 AM
        CXL interconnect specificationdmcq2019/03/12 02:20 AM
        CXL interconnect specificationAaron Spink2019/03/12 01:04 PM
          CXL interconnect specificationMichael S2019/03/13 03:32 AM
            ECC bit-stealing for coherence directoryPaul A. Clayton2019/03/13 07:45 AM
              Approximate directoryDavid Kanter2019/03/13 07:48 AM
                Approximate directoryAaron Spink2019/03/14 06:17 AM
              ECC bit-stealing for coherence directoryMichael S2019/03/13 08:31 AM
                ECC bit-stealing for coherence directoryAaron Spink2019/03/14 06:22 AM
              ECC bit-stealing for coherence directoryJeff S.2019/03/13 08:37 AM
                ECC bit-stealing for coherence directoryAaron Spink2019/03/14 06:24 AM
                  ECC bit-stealing for coherence directoryJeff S.2019/03/14 08:18 AM
                    ECC bit-stealing for coherence directoryaaron spink2019/03/15 12:28 AM
                      ECC bit-stealing for coherence directoryJeff S.2019/03/15 05:57 AM
                        ECC bit-stealing for coherence directoryaaron spink2019/03/15 09:32 PM
                          ECC bit-stealing for coherence directoryJeff S.2019/03/16 06:03 AM
                            ECC bit-stealing for coherence directoryaaron spink2019/03/16 05:58 PM
                  ECC bit-stealing for coherence directoryMichael S2019/03/14 08:25 AM
                    ECC bit-stealing for coherence directoryaaron spink2019/03/15 01:07 AM
                      ECC bit-stealing for coherence directoryMichael S2019/03/15 04:01 AM
                        Ivy Bridge-EX, Haswell-EPDavid Kanter2019/03/16 08:32 AM
                          Ivy Bridge-EX, Haswell-EPMichael S2019/03/17 05:31 AM
                            Memory directory in SKXTravis Downs2019/03/17 10:18 AM
                              Thank you. It's very interesting. (NT)Michael S2019/03/18 02:42 AM
                Linpack (McCalpin paper?) is not a motivation for directories (NT)Paul A. Clayton2019/03/14 06:25 PM
                ECC bit-stealing for coherence directoryTravis Downs2019/03/17 02:03 PM
                  Italics fail, sorry (NT)Travis Downs2019/03/17 02:03 PM
  CXL interconnect specificationRobert Williams2019/04/09 08:56 AM
    coherent memory poolsanonymous22019/04/09 01:04 PM
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