Lakefield Foveros

By: Maynard Handley (, April 22, 2019 7:53 pm
Room: Moderated Discussions
This is kinda late, but prompted by reading the most recent AnandTech article on Foveros and thinking about it. At first, like everyone else, I was caught up in the excitement of our glorious chiplet future. But with some time to reflect...

WHY is Intel pushing this tech?

Why would you design using chiplets rather than a single SoC? Under "normal" conditions, chiplets are going to be more expensive (packaging is never free) and more power (off chip, even via EMIB or interposer, is always more expensive than on-chip).

Some reasons that spring to mind:
- integrating very different technologies. This is, eg, the HBM issue, DRAM fabs are different from logic fabs.

- integrating IP from different companies. This is the Kaby-Lake G issue.

- you can't make a die the size you want. This is the AMD issue. It's not THAT interesting technically in that that's just a fancy PCB (much more expensive, much more performant); and the target market is much smaller. If the economics of yield rates vs interposer change, AMD shifts how they do multi-module vs larger die.

- OR the last reason, a variant of the first. To mix and match the same technology but at different nodes.

NOW let's ask the Intel question again. Why are they doing this? Well the only product they've told us about as using Foveros is Lakefield. Lakefield is a ~140mm^2 footprint. For reference, that's the same size as an A12X shipping on TSMC7nm.
Why use Foveros for this thing?
It's NOT that large.
It's NOT using fancy memory integration. (There is packaged DRAM, but just basic PoP like phones have been doing for years.)
It's not integrating foreign IP.
What it IS doing is creating some of the product on 10nm, and some on 22nm.

So why do that? Intel will tell you that it saves costs, or some other BS. I don't buy that at all.
Here's what I think is going on. It's basically another admission that 10nm has, uh, problematic, yields. The lousy yields mean Intel is building the bare minimum they have to on 10nm, which means a few small cores. What CAN be moved off chip (IO, PHYs, stuff like that) HAS been moved off, to shrink the 10nm die.

So I see this all as just one more part of Intel's ever-more-desperate EGOB, a desperate juggling of balls. Foveros is introduced as a great step forward, something that can do things current design can not. That's not actually true, not for a long while, but Intel has to keep extending the hype horizon to stay looking viable and leading edge.
Meanwhile they ALSO have to ship something, anything, in 10nm, to keep that ball in the air.
So marry the two! Use a basically inappropriate match (a design that would not make sense for Apple or QC, because it's more expensive and higher power than just making a properly designed SoC of the appropriate size) to allow shipping Lakefield in acceptable volumes, while at minimal die size! And as a bonus you can claim that you're doing something so awesome with new tech!

OK, so the Intel fans will all disagree, this is crazy. OK, sure, but ask yourselves:
- do you REALLY believe that it's cheaper to make two separate dies and package them together than to make a larger die? That goes against the economics of semiconductor logic that's held since the 70's. It only works if the cost of 10nm is astonishingly high compared to 22nm (which is another way of saying terrible yield).
- If this is not being done because of 10nm yield, then why is it being done? To save 100mm^2 area? Give me a break! 1sq cm is essential on a watch. It's nice (but inessential) on a phone. It's irrelevant on a laptop. If you're so starved for area in a laptop, even a really compact one, there are simpler options like the sandwiched PCB used by the iPhone X, and now by (I think) the newest Samsung phones.
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TopicPosted ByDate
Lakefield FoverosMaynard Handley2019/04/22 07:53 PM
  Lakefield FoverosMichael S2019/04/22 11:39 PM
    Lakefield FoverosBeastian2019/04/23 06:02 PM
      Lakefield FoverosMichael S2019/04/23 10:36 PM
  Lakefield FoverosRobert Williams2019/04/23 08:59 AM
  Lakefield FoverosEric Bron2019/04/24 02:14 AM
    Lakefield FoverosMaynard Handley2019/04/24 11:34 AM
      Lakefield Foverosanonymou52019/04/24 09:06 PM
      Lakefield FoverosEric Bron2019/04/26 06:58 AM
        Lakefield FoverosMaynard Handley2019/04/26 09:52 AM
          Lakefield FoverosEric Bron2019/04/26 10:40 AM
            Lakefield FoverosMaynard Handley2019/04/26 11:25 AM
              Lakefield FoverosEric Bron2019/04/26 02:34 PM
              Lakefield FoverosWilco2019/04/27 01:56 AM
    Lakefield FoverosAdrian2019/04/24 09:10 PM
  Lakefield FoverosYoav2019/04/24 05:46 AM
    Lakefield FoverosMaynard Handley2019/04/24 11:43 AM
      Lakefield Foverosme2019/04/25 11:53 AM
  Lakefield Foverosme2019/04/24 12:21 PM
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