Performance counter descriptions

By: Travis Downs (, May 6, 2019 8:24 am
Room: Moderated Discussions
Performance counter descriptions have been a good source of hints as to the internal microarchitecture of Intel CPUs, but it looks like some are being sanitized.

For example, RESOURCE_STALLS.ANY had this description:

Counts resource-related stall cycles. Reasons for stalls can be as follows:a. *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots).b. *any* u-arch structure got empty (like INT/SIMD FreeLists).c. FPU control word (FPCW), MXCSR.and others. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.

A very handy list of a presumably non-exhaustive structures that can become full or empty, including some that have basically zero public discussion like LM (load matrix), PRRT, etc.

The newest download just says:

Counts resource-related stall cycles.

So hold on to those old json files if you have them! only seems to keep the newest ones. The manuals never had the long descriptions in the first place.
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Performance counter descriptionsTravis Downs2019/05/06 08:24 AM
  Performance counter descriptionschester lam2019/05/06 01:29 PM
    Performance counter descriptionsMaynard Handley2019/05/06 05:17 PM
      Performance counter descriptionschester lam2019/05/09 01:44 PM
        Performance counter descriptionsMaynard Handley2019/05/09 03:01 PM
          Performance counter descriptionschester lam2019/05/09 04:42 PM
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