Performance counter descriptions

By: chester lam (lamchester.delete.delete@this.this.gmail.com), May 6, 2019 2:29 pm
Room: Moderated Discussions
Ok, I'm curious now. What are these structures? Searches just turn up obscure patents or nothing at all.
LM - from http://www.freepatentsonline.com/7958336.html, it's probably a dependency matrix for instructions that depend on loads.
PRRT - what is this??? https://patents.google.com/patent/US8707015 from AMD talks about reclaiming physical registers used by microcode. But if Intel uses the PRRT to track registers in use by microcode, I don't understand how a full PRRT would block FE uop delivery to the backend.
PHT - I can't find anything on this. Maybe it implements checkpointing to recover from mispredicts, and a slot is allocated for branches and loads.

I'm also confused by how the FPU control word and MXCSR are u-archs structures that block uop delivery if empty. They're just control registers that can also be renamed, right?

Travis Downs (travis.downs.delete@this.gmail.com) on May 6, 2019 9:24 am wrote:
> Performance counter descriptions have been a good source of hints as to the internal
> microarchitecture of Intel CPUs, but it looks like some are being sanitized.
>
> For example, RESOURCE_STALLS.ANY had this description:
>
>
>
>
Counts resource-related stall cycles. Reasons for stalls can be as follows:a. *any* u-arch structure got
> full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT)
> slots).b. *any* u-arch structure got empty (like INT/SIMD FreeLists).c. FPU control word (FPCW), MXCSR.and
> others. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.

>
> A very handy list of a presumably non-exhaustive structures that can become full or empty, including
> some that have basically zero public discussion like LM (load matrix), PRRT, etc.
>
> The newest download just says:
>
>
Counts resource-related stall cycles.

>
> So hold on to those old json files if you have them! 01.org only seems to keep
> the newest ones. The manuals never had the long descriptions in the first place.

< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Performance counter descriptionsTravis Downs2019/05/06 09:24 AM
  Performance counter descriptionschester lam2019/05/06 02:29 PM
    Performance counter descriptionsMaynard Handley2019/05/06 06:17 PM
      Performance counter descriptionschester lam2019/05/09 02:44 PM
        Performance counter descriptionsMaynard Handley2019/05/09 04:01 PM
          Performance counter descriptionschester lam2019/05/09 05:42 PM
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