Could EPYC/Rome have eDRAM L4? (as memory-side cache)

By: Heikki Kultala (heikki.kultala.delete@this.tuni.fi), June 11, 2019 4:37 am
Room: Moderated Discussions
I already though that "not going to happen", but then..

Latest information says that Ryzen's IO-chip is made on GF "12nm" process, but EPYCs IO-chip is made on "14nm" process.

Only reason I can think of why they would use "14nm" is that it's the IBM-derived 14HP and because of it's eDRAM support.

The cache would probably be organized as memory-side cache so no coherency protocol would be needed.


Based on POWER9 die photos, the density of the eDRAM should be something close to 1 mm^2 per MiB (including tags) ?

The IO chip is about close to 400 mm², so 128 MiB of eDRAM-L4 should consume about 128 mm², leaving still over 250 mm² for other stuff.

This could even be distributed into 8 separate 16 MiB caches, one for each memory controller, to make bus structure easier, though this would lower the hitrate.

And yes, there is already total of 256 MiBs of L3 caches, but 16 separate CPU-side 16-MiB caches means maximum of 16 MiB of data can be cached by any single thread into these L3 caches, and in worst case same data could be duplicated into 16 separate L3 caches, while having two sockets with 128MiB+128MiB of L4 memory-side cache can give all 256MiB L4 capacity for single thread, and same data could never be wasting space from multiple L4 caches no matter how many cores use it.













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TopicPosted ByDate
Could EPYC/Rome have eDRAM L4? (as memory-side cache)Heikki Kultala2019/06/11 04:37 AM
  TSMCAnon2019/06/11 05:56 AM
    TSMCuseruser2019/06/11 06:07 AM
    There is no TSMC "14nm" process. (NT)Heikki Kultala2019/06/11 06:27 AM
  Could EPYC/Rome have eDRAM L4? (as memory-side cache)Adrian2019/06/11 06:57 AM
    Could EPYC/Rome have eDRAM L4? (as memory-side cache)Poindexter2019/06/14 04:37 AM
      Could EPYC/Rome have eDRAM L4? (as memory-side cache)Wilco2019/06/14 12:51 PM
  There isn't roomWes Felter2019/06/11 10:45 AM
    a near pointless clarificationblue2019/06/12 09:50 AM
      a near pointless clarificationWes Felter2019/06/12 12:00 PM
  Could EPYC/Rome have eDRAM L4? (as memory-side cache)anon2019/06/11 12:08 PM
    Could EPYC/Rome have eDRAM L4? (as memory-side cache)Heikki Kultala2019/06/12 12:09 AM
      Could EPYC/Rome have eDRAM L4? (as memory-side cache)anon2019/06/12 03:58 AM
        Could EPYC/Rome have eDRAM L4? (as memory-side cache)Heikki Kultala2019/06/12 07:08 AM
          Could EPYC/Rome have eDRAM L4? (as memory-side cache)anon2019/06/12 08:58 AM
        Could EPYC/Rome have eDRAM L4? (as memory-side cache)Groo2019/06/12 11:40 AM
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