By: Simon Farnsworth (, July 5, 2019 1:51 am
Room: Moderated Discussions
anon ( on July 4, 2019 5:53 pm wrote:
> RichardC ( on July 4, 2019 10:54 am wrote:
> > Simon Farnsworth ( on July 4, 2019 9:46 am wrote:
> > > I think the decisions made to get from ARM2 to ARM3 are, with 20/20 hindsight, not right
> > > (VIVT cache in the ARM3, SWP and SWPB instead of a single CMPSWP instruction or an extremely
> > > constrained LDREX/STREX pair - one that fails the store if the CPU is interrupted during
> > > the critical sequence by anything, and a new bus line for "interrupt LDREX/STREX").
> >
> > IIRC I left Acorn in mid-1988, before ARM-3, so I don't have much insight into that and
> > later CPUs. The designers were cycle-counters and speed freaks, so that's probably why the
> > VIVT cache was favored.
> VIVT caches look really good to a hardware designer. I'm not sure what software looked like back then, but even
> today if you don't have a solid understanding of how the software stack works (OS and applications), then you
> could be forgiven for wondering why on anybody would use PT. Back then with much less experience of virtual memory,
> and the company writing their own OSes, VIVT was not a bad choice from what data they (likely) had.
Especially since there were no aliases of the same physical address in Acorn's hardware - the only aliases were in virtual space, and the ARM3's unified 4KiB cache was smaller than a page. Add in that MEMC was configured by address writes only (it wasn't even connected to the data lines), and it wouldn't have looked obvious that VIVT was a mistake; the CPU would know that it was writing to MEMC's logical to physical translation map by address alone, and it's easy to imagine that the cache could detect this and flush all cache lines that match the logical address that's having its translation changed. After all, the cache sees all reads and writes to begin with - you can architecturally define that the cache works with MEMC translation configs alone.

> IMO it falls in the category of something like a trace cache. It looks very good from a lot of angles
> and even many of the angles where it does not look so good in isolation have a number of apparent software
> and hardware mitigations. It's only when you have worked through the problems and have an understanding
> of the entire system that you might come to decide that it is not the best approach.

I think you'd also need a more sophisticated MMU than MEMC1 - it only allows each physical page to map to one virtual address, so alias handling isn't challenging. It's only when you need to track physical aliases that VIVT caches become intractably hard.
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TopicPosted ByDate
ARM1/ARM2 Alternative? (20/20 Hindsight)Paul A. Clayton2019/06/27 05:47 PM
  ARM1/ARM2 Alternative? (20/20 Hindsight)Maxwell2019/06/27 08:10 PM
    ARM1/ARM2 Alternative? (20/20 Hindsight)Paul A. Clayton2019/06/28 11:44 AM
      ARM1/ARM2 Alternative? (20/20 Hindsight)RichardC2019/07/03 07:56 PM
        ARM1/ARM2 Alternative? (20/20 Hindsight)Simon Farnsworth2019/07/04 04:09 AM
          DMARichardC2019/07/04 05:52 AM
            DMASimon Farnsworth2019/07/04 09:46 AM
              DMARichardC2019/07/04 10:54 AM
                DMAanon2019/07/04 05:53 PM
                  DMASimon Farnsworth2019/07/05 01:51 AM
                  DMARichardC2019/07/05 08:24 PM
            DMAMaxwell2019/07/04 09:49 AM
              DMAHoward Chu2019/07/04 10:55 AM
              DMARichardC2019/07/04 11:00 AM
          ARM1/ARM2 Alternative? (20/20 Hindsight)Etienne2019/07/04 08:06 AM
            ok once you have MMURichardC2019/07/04 08:46 AM
  ARM1/ARM2 Alternative? (20/20 Hindsight)Etienne2019/06/28 01:52 AM
  ARM1/ARM2 Alternative? (20/20 Hindsight)jv2019/06/28 07:20 AM
    ARM1/ARM2 Alternative? (20/20 Hindsight)Paul A. Clayton2019/06/28 11:44 AM
      ARM1/ARM2 Alternative? (20/20 Hindsight)jv2019/06/29 03:54 AM
        Freeing the stack pointerPaul A. Clayton2019/06/29 06:32 AM
          PC-relative LD/ST (NT)vvid2019/06/30 10:03 AM
          Freeing the stack pointerjv2019/06/30 11:45 PM
  ARM1/ARM2 Alternative? (20/20 Hindsight)Ronald Maas2019/06/28 09:06 AM
    ARM1/ARM2 Alternative? (20/20 Hindsight)Paul A. Clayton2019/06/28 12:56 PM
      ARM1/ARM2 Alternative? (20/20 Hindsight)Ronald Maas2019/06/28 10:17 PM
        ARM1/ARM2 Alternative? (20/20 Hindsight)Brett2019/06/29 12:39 AM
          ARM1/ARM2 Alternative? (20/20 Hindsight)Brett2019/06/29 01:13 AM
          32-bit Win10 exists (NT)nobody in particular2019/06/29 05:17 PM
            32-bit Win10 existsBrett2019/06/29 06:45 PM
              32-bit Win10 existsMichael S2019/06/30 01:34 AM
                32-bit Win10 existsAnon32019/06/30 03:07 AM
        AArch64 is a new ISAPaul A. Clayton2019/06/29 07:23 AM
          AArch64 is a new ISArwessel2019/06/29 04:00 PM
            AArch64 is a new ISAMichael S2019/06/30 01:40 AM
              Hardware x87?Gionatan Danti2019/06/30 02:22 AM
                Hardware x87?Michael S2019/06/30 03:52 AM
                  Hardware x87?Gionatan Danti2019/06/30 06:04 AM
                    Hardware x87?Michael S2019/06/30 08:47 AM
                  Hardware x87?Kevin G2019/07/01 12:11 PM
                    Hardware x87?anonymou52019/07/01 07:30 PM
                      Hardware x87?Michael S2019/07/02 12:44 AM
                      Hardware x87?Gionatan Danti2019/07/02 09:25 AM
              AArch64 is a new ISArwessel2019/06/30 01:52 PM
            AArch64 is a new ISAMichael S2019/06/30 01:42 AM
        ARM1/ARM2 Alternative? (20/20 Hindsight)Maynard Handley2019/06/29 09:50 AM
        ARM1/ARM2 Alternative? (20/20 Hindsight)Michael S2019/06/30 01:29 AM
          ARM1/ARM2 Alternative? (20/20 Hindsight)Wilco2019/06/30 03:51 AM
            ARM1/ARM2 Alternative? (20/20 Hindsight)Michael S2019/06/30 04:22 AM
              ARM1/ARM2 Alternative? (20/20 Hindsight)Wilco2019/06/30 05:27 AM
                ARM1/ARM2 Alternative? (20/20 Hindsight)Michael S2019/06/30 05:53 AM
                  ARM1/ARM2 Alternative? (20/20 Hindsight)Wilco2019/07/02 01:49 AM
                    ARM1/ARM2 Alternative? (20/20 Hindsight)Michael S2019/07/02 04:24 AM
                      ARM1/ARM2 Alternative? (20/20 Hindsight)Wilco2019/07/02 05:28 PM
                        ARM1/ARM2 Alternative? (20/20 Hindsight)Michael S2019/07/03 01:37 AM
                          ARM1/ARM2 Alternative? (20/20 Hindsight)Adrian2019/07/03 02:45 AM
                            ARM1/ARM2 Alternative? (20/20 Hindsight)Michael S2019/07/03 03:01 AM
                            ARM1/ARM2 Alternative? (20/20 Hindsight)Montaray Jack2019/07/03 12:18 PM
                              ARM1/ARM2 Alternative? (20/20 Hindsight)Montaray Jack2019/07/03 01:46 PM
                        ARM1/ARM2 Alternative? (20/20 Hindsight)Montaray Jack2019/07/03 02:32 PM
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