RISC-V base ISA ratified

By: Gabriele Svelto (gabriele.svelto.delete@this.gmail.com), July 12, 2019 11:04 am
Room: Moderated Discussions
As per title: RISC-V Foundation Announces Ratification of the RISC-V Base ISA and Privileged Architecture Specifications

In related news the last RISC-V workshop proceedings have been published a few weeks ago here. Some interesting highlights:

Bit by bit - How to fit 8 RISC-V cores in a $38 FPGA board (a RISC-V bit-serial implementation)

Better Living Through Bit ManipulationHigher Performance at Lower Power - RISC-V BitManip Task Group (bit-manipulation extensions)

Status update of RISC-V P extension task group (AKA packed SIMD extensions)

Vector Extension Update

The latter has an interesting addition compared to the last time I checked it: the physical width of cross-lane operations (e.g. element permutations, reductions, etc...). This allows to generalize algorithms that rely on that type of instructions which couldn't be captured simply by the vector length.
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RISC-V base ISA ratifiedGabriele Svelto2019/07/12 11:04 AM
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