RISC-V base ISA ratified

By: Montaray Jack (none.delete@this.none.org), July 13, 2019 4:39 pm
Room: Moderated Discussions
Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on July 12, 2019 11:04 am wrote:
> As per title: RISC-V Foundation Announces Ratification of the
> RISC-V Base ISA and Privileged Architecture Specifications

>
> In related news the last RISC-V workshop proceedings have been
> published a few weeks ago here. Some interesting highlights:
>
> Bit by bit - How to fit 8 RISC-V cores in a $38 FPGA board (a RISC-V bit-serial implementation)
>
> Better Living Through Bit ManipulationHigher Performance at Lower
> Power - RISC-V BitManip Task Group
(bit-manipulation extensions)
>
> Status update of RISC-V P extension task group (AKA packed SIMD extensions)
>
> Vector Extension Update
>
> The latter has an interesting addition compared to the last time I checked it: the physical width of
> cross-lane operations (e.g. element permutations, reductions, etc...). This allows to generalize algorithms
> that rely on that type of instructions which couldn't be captured simply by the vector length.

It's interesting how modern memory systems with cache and virtual memory adversely affect vector chaining, in contrast to the lockstep access to memory banks that the Cray 1 had.

https://content.riscv.org/wp-content/uploads/2019/03/11.35-RISCV-WORKSHOP-TAIWAN-SLIDE-SIMULATION-CHAINING.pdf
https://www.youtube.com/watch?v=0Uph96-21Eg
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RISC-V base ISA ratifiedGabriele Svelto2019/07/12 11:04 AM
  RISC-V base ISA ratifiedMontaray Jack2019/07/13 04:39 PM
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