ARM Flexible Access and RISC-V

By: Gabriele Svelto (gabriele.svelto.delete@this.gmail.com), July 29, 2019 1:40 pm
Room: Moderated Discussions
Not long ago ARM announced a pretty drastic change in the way the IP for their MCU-class designs are licensed which they called flexible access.

In a nutshell customers are allowed access to ARM IP before paying a license for it (what ARM calls a "per product license"). This allows the customer to fully design its product using ARM IP without any upfront costs - and with the ability of experimenting with different solutions - and only pay up when comes the time for the design to hit the fab.

If you've been following the evolution of RISC-V commercial efforts this won't sound like a new development: it's basically SiFive's DesignShare program with a different name.

So this all sounds like ARM's reaction to the changes the RISC-V ecosystem is bringing to the market. However it's the timing that surprised me. SiFive recently announced having reached a 100 design wins for their IP which is not really a large number. There's quite a few other vendors offering commercial RISC-V cores and associated IP but none of them are really huge. So I'm left wondering if this is a preventive move on ARM's part or if RISC-V has already made a bigger dent in the market than I thought.

It might also be possible that Flexible Access is not a reaction to commercial RISC-V offerings but to RISC-V in general. Some of the latest free/open-source cores are quite capable and they come with a lot more IP than the core itself. For example Western Digital not only released SweRV but also it's cache-coherent interconnect OmniXtend. SweRV has also been picked up by others (and improvements were upstreamed!). So maybe ARM realized that their IP needs to be more readily accessible if they want to compete in the long run.

Either way I think it's fair to say that RISC-V has already succeeded in changing how hardware gets designed.
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ARM Flexible Access and RISC-V Gabriele Svelto2019/07/29 01:40 PM
  ARM Flexible Access and RISC-V anonymous22019/07/29 03:14 PM
    ARM Flexible Access and RISC-V dmcq2019/07/30 06:55 AM
  ARM Flexible Access and RISC-V dmcq2019/07/30 06:35 AM
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