ICL memory renaming?

By: Travis Downs (travis.downs.delete@this.gmail.com), August 2, 2019 6:43 pm
Room: Moderated Discussions
Here's an interesting block from the recent ICL InstlatX64 dump:

34 X86 :MOV r8,[m8]+MOV [m8],r8 L: 0.78ns= 1.0c T: 0.60ns= 0.77
35 X86 :MOV r16,[m16]+MOV [m16],r16 L: 9.24ns= 11.8c T: 0.35ns= 0.45
36 X86 :MOV r32,[m32]+MOV [m32],r32 L: 0.40ns= 0.5c T: 1.06ns= 1.35
37 AMD64 :MOV r64,[m64]+MOV [m64],r64 L: 0.44ns= 0.6c T: 0.61ns= 0.78
Assuming I understand the notation correctly these are load-store pairs to the same location, where the stored value comes from the prior load. Something like:
mov eax, [rdx]
mov [rdx], eax
repeat...


On dumps from existing Intel CPUs, or Zen and Zen2, these are always in the range of 10-20 cycles. However, the results above show that except for the 16-bit variant, the times are 1 cycle or less. For the 32-bit cases, the latency is less than the throughput. It seems there is some magic that recognizes the identical memory location and allows this to resolve perhaps right at rename, similarly to an eliminated move.

I haven't seen any hints of this before. Has anyone heard anything?
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TopicPosted ByDate
ICL memory renaming?Travis Downs2019/08/02 06:43 PM
  ICL memory renaming?anonlitmus2019/08/03 07:06 AM
    ICL memory renaming?Travis Downs2019/08/04 02:55 PM
      ICL memory renaming?anonlitmus2019/08/04 03:20 PM
        ICL memory renaming?Travis Downs2019/08/04 04:51 PM
  ICL memory renaming?ll2019/08/03 08:37 PM
    ICL memory renaming?Montaray Jack2019/08/03 11:53 PM
      ICL memory renaming?Montaray Jack2019/08/04 12:44 AM
    ICL memory renaming?Travis Downs2019/08/04 03:00 PM
      ICL memory renaming?ll2019/08/05 06:05 AM
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