ICL memory renaming?

By: anonlitmus (anon.delete@this.litmus.org), August 3, 2019 7:06 am
Room: Moderated Discussions
10-20 cycles seems too much for something that is a clear-cut Store-to-Load forwarding case. In steady state it should be more or less similar to L1D hit, shouldn't it (see some oldish data at http://blog.stuffedcow.net/2014/01/x86-memory-disambiguation/)?

Also, any idea why the 16-bit version would be slower than the 8/32/64-bit version? I am guessing that it is the partial register semantics that makes it not memory rename-able but then the 8-bit case should have the same issue, right?
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ICL memory renaming?Travis Downs2019/08/02 06:43 PM
  ICL memory renaming?anonlitmus2019/08/03 07:06 AM
    ICL memory renaming?Travis Downs2019/08/04 02:55 PM
      ICL memory renaming?anonlitmus2019/08/04 03:20 PM
        ICL memory renaming?Travis Downs2019/08/04 04:51 PM
  ICL memory renaming?ll2019/08/03 08:37 PM
    ICL memory renaming?Montaray Jack2019/08/03 11:53 PM
      ICL memory renaming?Montaray Jack2019/08/04 12:44 AM
    ICL memory renaming?Travis Downs2019/08/04 03:00 PM
      ICL memory renaming?ll2019/08/05 06:05 AM
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