Xilinx Versal series - how many dies?

By: Michael S (already5chosen.delete@this.yahoo.com), August 12, 2019 3:37 am
Room: Moderated Discussions
Jason Creighton (noreply.delete@this.example.com) on August 11, 2019 5:19 pm wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on August 11, 2019 1:57 pm wrote:
> > I am trying to understand technology behind Xilinx new Versal series of adaptive compute acceleration
> > platform (ACAP), but so far unable to find any information on how it is built internally.
> > Is it one enormous (> 1000 mm^2) die ? Or several (2-3) dies? Or many dies?
> In recent previous generations (7-series, UltraScale, and UltraScale+), the smaller/medium-sized
> FPGAs are monolithic, and larger FPGAs are composed of multiple dies (but not a huge number,
> the largest I'm aware of is 4 dies), which Xilinx calls SLRs ("Super Logic Region")

Thank you.
The only 7-series device I touched myself was Zync. I suppose, it qualifies as smaller/medium-sized.

> This is not transparent to the user: If you are using one of these multi-die parts,
> you have to floorplan which logic is going in which SLR if you want good timing
> closure, so a monolithic part is better if you can live with the size.
> You can see their marketing information here, they call them '3D ICs', although I personally find that
> misleading, as they do not stack the logic dies, they arrange them in a planar fashion on an interposer.

Thank you.
It took time, but finally I found a table that shows # of SRLs per device.
It says that the biggest device, VU440, consist of 3 SLRs. The only device consisting of 4 SLRs is smaller VU13P.

Hopefully, similar table for Versal series will be published soon.
The FPGA fabric part of Versal does not look particularly big, but high-end parts contains a lot of SRAM. If it would be split into several dies then an interesting question is "will all SLRs contain all sorts of processing engines?"

> I have not dug too deep into Versal, but my guess would be that they are doing the same thing there.
> And AFAIK although they decided to rebrand Versal as an "ACAP" instead of an FPGA, really
> the only novel thing in Versal is the AI engines, which is a grid of VLIW SIMD processors.
> (See the AI Engine whitepaper) Everything else is pretty similar to UltraScale+.
> Another interesting choice they made with Versal is that all Versal parts will be SoCs: You don't
> have to use them, but all Versals will have dual Cortex A72s, a hard memory controller, etc.

Hopefully, at that scale Dual-ARM Cortex-A72 is very small relatively to the rest of the chip. It's not like Intel's CPU where half of the chip is GPU which is used to its full capacity by small fraction of the buyers.
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Xilinx Versal series - how many dies?Michael S2019/08/11 01:57 PM
  Xilinx Versal series - how many dies?Jason Creighton2019/08/11 05:19 PM
    Xilinx Versal series - how many dies?Michael S2019/08/12 03:37 AM
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