Intel Tremont

By: Adrian (a.delete@this.acm.org), October 24, 2019 11:46 am
Room: Moderated Discussions


Finally some information about the successor of Goldmont Plus.


https://newsroom.intel.com/news/intel-introduces-tremont-microarchitecture/




Among the interesting features:


6-wide OoO instruction decode (in 2 clusters) without the area penalty of a uOp cache


Accelerator interfacing instructions: efficient and scalable work dispatch and synchronization to accelerators


Up to 30% better IPC than Goldmont Plus, but unknown clock frequencies, maybe lower
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