Risc-V getting real?

By: Anon (no.delete@this.thanks.com), October 31, 2019 3:10 pm
Room: Moderated Discussions
SiFive are pushing the boat out a little further with U8 - OOO RISC-V with performance that is starting to look like less of a toy? (not that I dislike it, it certainly seems to fit a fair number of applications).

And of course they are also playing the ML game.. like everyone seems to be now.


Anandtech is not exactly my choice for such information, but an easy light read.
https://www.anandtech.com/show/15036/sifive-announces-first-riscv-ooo-cpu-core-the-u8series-processor-ip

https://www.sifive.com/press/sifive-announces-new-u8-series-core-ip-for-high-performance

And others are playing similar games:

https://www.seeedstudio.com/Sipeed-M1-dock-suit-M1-dock-2-4-inch-LCD-OV2640-K210-Dev-Board-1st-RV64-AI-board-for-Edge-Computing.html

Risc-V does seem to be gaining inertia as a platform for 'giving things a try', which is.... refreshing?


The SiFive manuals still seem... light? I have not looked close enough to see if they address the all too common issue of many ARM implementations whereby there is not quite enough information to actually use them without near impossible Chinese NDA/IP agreements (although that does seem to be slowly improving).
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Risc-V getting real?Anon2019/10/31 03:10 PM
  Risc-V getting real?Gabriele Svelto2019/11/01 03:28 AM
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      Risc-V getting real?lockederboss2019/11/02 01:49 AM
      Risc-V getting real?Gabriele Svelto2019/11/03 02:20 AM
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        Risc-V getting real?anon2019/11/03 08:29 PM
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        Risc-V getting real?dmcq2019/11/04 06:41 AM
    Documentation QualityKonrad Schwarz2019/11/04 05:43 AM
      Documentation QualityGabriele Svelto2019/11/04 06:31 AM
        Documentation QualityAnon2019/11/04 12:28 PM
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                RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/03 10:06 AM
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                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 07:13 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 09:58 AM
                    RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 09:57 AM
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                        RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 10:48 AM
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              The RISC-V bitmanip ISA extension has conditional movesWilco2019/11/03 06:38 AM
                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds2019/11/03 10:03 AM
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:29 AM
                  The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:38 AM
                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 07:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 09:36 AM
                            I'm glad you're not that blind :) (NT)none2019/11/04 09:36 AM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:23 AM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 06:16 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 11:42 PM
                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 06:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 06:04 PM
                                  The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 02:21 AM
                                    The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 03:31 AM
                                    The RISC-V bitmanip ISA extension has conditional movesKonrad Schwarz2019/11/06 07:03 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 07:57 AM
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 08:55 AM
                      The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 07:24 AM
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                          The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 05:02 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 11:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesnone2019/11/05 12:45 AM
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                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 01:12 AM
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 02:22 AM
                                      The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 02:44 AM
                                        The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 02:50 AM
                                        The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 03:08 AM
                                          The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 07:24 AM
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                                      The RISC-V bitmanip ISA extension has conditional movesnoko2019/11/06 11:07 AM
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                              The RISC-V bitmanip ISA extension has conditional movesj2019/11/05 01:43 AM
                          The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/04 05:39 PM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 06:25 PM
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                      RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 11:03 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/04 11:27 AM
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                            RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/04 03:08 PM
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                  Flags RegisterWilco2019/11/04 02:49 PM
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                    Flags RegisterDavid Hess2019/11/05 04:35 PM
                      Flags RegisterWilco2019/11/05 05:54 PM
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                          Flags RegisterMaynard Handley2019/11/07 02:42 PM
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      RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 10:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 10:59 AM
          RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 11:11 AM
            RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 11:17 AM
              RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 11:54 AM
                RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/05 07:17 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/05 12:39 PM
                    RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/06 12:19 PM
                      RISC-V - incompetitive instruction set compared to ARMv8Doug S2019/11/06 12:47 PM
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                          RISC-V - incompetitive instruction set compared to ARMv8TREZA2019/11/07 01:31 PM
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                        RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/06 10:36 PM
                          The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 12:53 AM
                            Both are excellent ISAs ?Michael S2019/11/07 01:58 AM
                            The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/07 05:33 AM
                              The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 08:31 AM
                            The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/07 09:38 AM
                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 02:32 AM
                            The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 06:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/07 07:50 PM
                                The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 10:47 PM
                                  The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/08 03:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/08 06:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesDavid Hess2019/11/08 08:28 PM
                                      The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/08 09:14 PM
                      RISC-V - incompetitive instruction set compared to ARMv8G. Boniface2019/11/07 06:59 AM
                        Op fusion and superscalar execution do NOT share same hardwareHeikki Kultala2019/11/07 08:39 AM
                          Op fusion and superscalar execution do NOT share same hardwareRonald Maas2019/11/07 09:29 AM
                            Op fusion and superscalar execution do NOT share same hardwareanon2019/11/07 09:37 AM
                            Op fusion and superscalar execution do NOT share same hardwareWilco2019/11/07 12:41 PM
                            Op fusion and superscalar execution do NOT share same hardwareFoo_2019/11/07 12:42 PM
                              Op fusion and superscalar execution do NOT share same hardwareanon.12019/11/07 11:00 PM
                    RISC-V - incompetitive instruction set compared to ARMv8wumpus2019/11/06 05:19 PM
              RISC-V - conditional branches are problematic tooWilco2019/11/04 02:31 PM
                reg-reg branchesMichael S2019/11/06 02:37 AM
                  reg-reg branchesWilco2019/11/07 05:55 PM
      RISC-V - incompetitive instruction set compared to ARMv8Montaray Jack2019/11/08 02:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 07:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 08:12 AM
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