Trivium: Andy Glew works for SiFive

By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), November 1, 2019 9:51 am
Room: Moderated Discussions
Anon (no.delete@this.thanks.com) on October 31, 2019 3:10 pm wrote:
> SiFive are pushing the boat out a little further with U8 - OOO RISC-V with performance that is starting to
> look like less of a toy? (not that I dislike it, it certainly seems to fit a fair number of applications).

Since SiFive recently hired Andy Glew as "Principal Engineer/Architect", the company's goals may be for more interesting microarchitectures.

[snip]
> Risc-V does seem to be gaining inertia as a platform for 'giving things a try', which is.... refreshing?

I am a little disappointed with the RISC-V architecture (even ignoring just being a RISC architecture). The architectural design seems to have suffered from "worse is better" in some areas and catherdral-like isolation in others. The worse-is-better defects seem understandable given the rush from local academic tool, to general academic tool, to industrial adoption. An academic tool has lower compatibility pressure, so planning to throw one interface specification away is not unreasonable. The defects of isolation seem to result from limited resources, attempts to partition concerns for constraining communication, and commercial interests increasing secrecy. These are understandable, but my idealistic tendencies would wish for better.
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Risc-V getting real?Anon2019/10/31 02:10 PM
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        Risc-V getting real?dmcq2019/11/04 05:41 AM
    Documentation QualityKonrad Schwarz2019/11/04 04:43 AM
      Documentation QualityGabriele Svelto2019/11/04 05:31 AM
        Documentation QualityAnon2019/11/04 11:28 AM
  Trivium: Andy Glew works for SiFivePaul A. Clayton2019/11/01 09:51 AM
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                RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/03 09:06 AM
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                    RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/04 06:03 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 06:13 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 08:58 AM
                    RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 08:57 AM
                      RISC-V - incompetitive instruction set compared to ARMv8rwessel2019/11/04 09:25 AM
                        RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 09:48 AM
                RISC-V - incompetitive instruction set compared to ARMv8Wilco2019/11/03 11:09 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas2019/11/03 09:44 PM
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              The RISC-V bitmanip ISA extension has conditional movesWilco2019/11/03 05:38 AM
                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds2019/11/03 09:03 AM
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 05:29 AM
                  The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 05:38 AM
                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 05:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 05:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 08:36 AM
                            I'm glad you're not that blind :) (NT)none2019/11/04 08:36 AM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 09:23 AM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 05:16 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:42 PM
                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 05:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 05:04 PM
                                  The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 01:21 AM
                                    The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 02:31 AM
                                    The RISC-V bitmanip ISA extension has conditional movesKonrad Schwarz2019/11/06 06:03 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 06:57 AM
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 07:55 AM
                      The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 06:24 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 03:07 PM
                          The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 04:02 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 11:45 PM
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                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 01:22 AM
                                      The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 01:44 AM
                                        The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 01:50 AM
                                        The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 02:08 AM
                                          The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 06:24 AM
                                      The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 04:53 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnoko2019/11/06 10:07 AM
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                              The RISC-V bitmanip ISA extension has conditional movesj2019/11/05 12:43 AM
                          The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/04 04:39 PM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 05:25 PM
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                      RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 10:03 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/04 10:27 AM
                          RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 11:07 AM
                          RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 12:22 PM
                            RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/04 02:08 PM
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        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 09:59 AM
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            RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 10:17 AM
              RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 10:54 AM
                RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/05 06:17 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/05 11:39 AM
                    RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/06 11:19 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Doug S2019/11/06 11:47 AM
                        RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/06 06:36 PM
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                          RISC-V - incompetitive instruction set compared to ARMv8TREZA2019/11/07 12:31 PM
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                        RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/06 09:36 PM
                          The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/06 11:53 PM
                            Both are excellent ISAs ?Michael S2019/11/07 12:58 AM
                            The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/07 04:33 AM
                              The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 07:31 AM
                            The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/07 08:38 AM
                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 01:32 AM
                            The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 05:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/07 06:50 PM
                                The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 09:47 PM
                                  The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/08 02:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/08 05:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesDavid Hess2019/11/08 07:28 PM
                                      The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/08 08:14 PM
                      RISC-V - incompetitive instruction set compared to ARMv8G. Boniface2019/11/07 05:59 AM
                        Op fusion and superscalar execution do NOT share same hardwareHeikki Kultala2019/11/07 07:39 AM
                          Op fusion and superscalar execution do NOT share same hardwareRonald Maas2019/11/07 08:29 AM
                            Op fusion and superscalar execution do NOT share same hardwareanon2019/11/07 08:37 AM
                            Op fusion and superscalar execution do NOT share same hardwareWilco2019/11/07 11:41 AM
                            Op fusion and superscalar execution do NOT share same hardwareFoo_2019/11/07 11:42 AM
                              Op fusion and superscalar execution do NOT share same hardwareanon.12019/11/07 10:00 PM
                    RISC-V - incompetitive instruction set compared to ARMv8wumpus2019/11/06 04:19 PM
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                reg-reg branchesMichael S2019/11/06 01:37 AM
                  reg-reg branchesWilco2019/11/07 04:55 PM
      RISC-V - incompetitive instruction set compared to ARMv8Montaray Jack2019/11/08 01:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 06:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 07:12 AM
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