By: Michael S (already5chosen.delete@this.yahoo.com), November 3, 2019 3:03 am
Room: Moderated Discussions
Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on November 3, 2019 1:20 am wrote:
> anon (anon.delete@this.anon.com) on November 2, 2019 1:46 am wrote:
> > If that is arguable then you should have some sources with evidence to show how widespread it
> > is. I have not heard anything much except quite a few companies looking at it, and some (WD)
> > looking to move their controllers to it. Haven't heard how far along those efforts are.
>
> Western Digitial has already started using RISC-V across multiple products,
> not only the opened up their designs but also their CC fabric (link).
>
> nVidia is using RISC-V controllers both in their GPUs and in other products (link).
>
> Those were just the most visible use case but most of RISC-V uses are to replace custom cores such as the ones
> sold by Tensilica. Practically every vendor of RISC-V cores (Andes, Codasip, Syntacore, IQonIC) is offering
> customized cores for roles such as DSPs, C&C and other forms of hardware acceleration. Those aren't general
> purpose cores so you won't find them in SoCs running a GP OS but they're shipping in products nonetheless.
>
> > Also what does "deeply" embedded mean?
>
> It means that the core is shipped within an ASIC that is not available for sale outside of the companies
> products. I.e. it's not a stand-alone product that you can buy for other applications such as a mobile
> SoC. WD and nVidia uses are very good examples. You can buy a WD SSD which will have RISC-V cores
> in its controller, but the controller itself won't be available as a stand-alone product.
My main problem with RISC-V is that it is strictly worse than MIPS (Release 6).
In comparison with aarch64 one can say, at least, "Yes, it's not as good, but so much simpler!".
Vs MIPSr6, fixed width variant of RV is not much worse, but it is worse in every single aspect where they differ. And equal in complexity.
As to compressed variant, it is better than MIPSr6 counterpart, but *much* worse than nano-MIPS. May be, it's simpler than nano-MIPS, I don't know, so far I didn't find time and motivation to look into details.
> anon (anon.delete@this.anon.com) on November 2, 2019 1:46 am wrote:
> > If that is arguable then you should have some sources with evidence to show how widespread it
> > is. I have not heard anything much except quite a few companies looking at it, and some (WD)
> > looking to move their controllers to it. Haven't heard how far along those efforts are.
>
> Western Digitial has already started using RISC-V across multiple products,
> not only the opened up their designs but also their CC fabric (link).
>
> nVidia is using RISC-V controllers both in their GPUs and in other products (link).
>
> Those were just the most visible use case but most of RISC-V uses are to replace custom cores such as the ones
> sold by Tensilica. Practically every vendor of RISC-V cores (Andes, Codasip, Syntacore, IQonIC) is offering
> customized cores for roles such as DSPs, C&C and other forms of hardware acceleration. Those aren't general
> purpose cores so you won't find them in SoCs running a GP OS but they're shipping in products nonetheless.
>
> > Also what does "deeply" embedded mean?
>
> It means that the core is shipped within an ASIC that is not available for sale outside of the companies
> products. I.e. it's not a stand-alone product that you can buy for other applications such as a mobile
> SoC. WD and nVidia uses are very good examples. You can buy a WD SSD which will have RISC-V cores
> in its controller, but the controller itself won't be available as a stand-alone product.
My main problem with RISC-V is that it is strictly worse than MIPS (Release 6).
In comparison with aarch64 one can say, at least, "Yes, it's not as good, but so much simpler!".
Vs MIPSr6, fixed width variant of RV is not much worse, but it is worse in every single aspect where they differ. And equal in complexity.
As to compressed variant, it is better than MIPSr6 counterpart, but *much* worse than nano-MIPS. May be, it's simpler than nano-MIPS, I don't know, so far I didn't find time and motivation to look into details.
