By: Gabriele Svelto (gabriele.svelto.delete@this.gmail.com), November 3, 2019 4:45 am
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on November 3, 2019 2:03 am wrote:
> My main problem with RISC-V is that it is strictly worse than MIPS (Release 6).
> In comparison with aarch64 one can say, at least, "Yes, it's not as good, but so much simpler!".
> Vs MIPSr6, fixed width variant of RV is not much worse, but it is worse
> in every single aspect where they differ. And equal in complexity.
> As to compressed variant, it is better than MIPSr6 counterpart, but *much* worse than nano-MIPS. May be, it's
> simpler than nano-MIPS, I don't know, so far I didn't find time and motivation to look into details.
Code density is a problem indeed and there's been new proposals to improve compression. The bitmanip extension is also going to increase code density in a number of workloads. A lot of cores are also shipping with non-standard extensions that are geared toward both higher performance and higher code-density in small implementations (there's a good overview in the Andes Extended Features presentation from the 2017 RISC-V workshop).
There's been efforts to improve area efficiency in soft implementations as well (see the Zfinx extension).
The MIPS open license and availability of the microAptiv is certainly heating up the competition.
> My main problem with RISC-V is that it is strictly worse than MIPS (Release 6).
> In comparison with aarch64 one can say, at least, "Yes, it's not as good, but so much simpler!".
> Vs MIPSr6, fixed width variant of RV is not much worse, but it is worse
> in every single aspect where they differ. And equal in complexity.
> As to compressed variant, it is better than MIPSr6 counterpart, but *much* worse than nano-MIPS. May be, it's
> simpler than nano-MIPS, I don't know, so far I didn't find time and motivation to look into details.
Code density is a problem indeed and there's been new proposals to improve compression. The bitmanip extension is also going to increase code density in a number of workloads. A lot of cores are also shipping with non-standard extensions that are geared toward both higher performance and higher code-density in small implementations (there's a good overview in the Andes Extended Features presentation from the 2017 RISC-V workshop).
There's been efforts to improve area efficiency in soft implementations as well (see the Zfinx extension).
The MIPS open license and availability of the microAptiv is certainly heating up the competition.