Adrian (a.delete@this.acm.org) on November 2, 2019 9:33 am wrote:
> Ronald Maas (ronaldjmaas.delete@this.gmail.com) on November 2, 2019 10:02 am wrote:
> > Heikki Kultala (heikki.kultala.delete@this.tuni.fi) on November 2, 2019 2:31 am wrote:
> > > And then ARMv8 has smart non-riscy things like:
> > >
> > > * More advanced addressing modes
> > > * Paired loads and stores
> > >
> > > Which can save huge amount of instructions.
> > >
> >
> > Someone from the RISC-V team made a video comparing various ISAs
> >
> > The diagram on the 18:30 mark shows RV64G requires 10% more instructions compared to ARMv8.
> >
> > Not a huge difference in my opinion.
> >
> > Ronald
> >
>
>
>
> That might be true for whole programs, but for critical loops it is not uncommon for RISC-V to need
> a double number of instructions compared to better instruction sets, e.g. ARMv8, x86 or POWER.
>
> The answer to that of the RISC-V architects is that any high-performance
> implementation of RISC-V must do instruction-pair fusion.
>
>
> I refuse to believe to believe that instruction-pair fusion is simpler or better than the
> trivial enhancement of the instruction encoding to cover the more complex instructions that
> are needed in almost all loops, e.g. either with indexed or auto-indexed addressing.
>
>

Are there any implementations out there which do macro op fusion and yes which pairs / idioms do they support ?
I can't remember whether Rocket or BOOM do it.