The RISC-V bitmanip ISA extension has conditional moves

By: Linus Torvalds (torvalds.delete@this.linux-foundation.org), November 3, 2019 10:03 am
Room: Moderated Discussions
Wilco (wilco.dijkstra.delete@this.ntlworld.com) on November 3, 2019 5:38 am wrote:
> Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on November 3, 2019 1:25 am wrote:
> > I hope that settles it since it comes up in each and every RISC-V discussion.
>
> It's just a proposal at this point. The extension is quite large and consists of several
> optional parts, so it isn't obvious whether conditional moves will ever be added. Even
> then it isn't obvious the extension will ever be used in implementations which would
> benefit the most (ie. lower-end ones with no or basic branch predictors).

That also shows the fundamental ugly side of the whole RISC-V "everything is an extension".

Many of the suggestions look very useful, but look at rotate vs shift-double ("funnel shift").

Rotate could just be implemented as a shift-double with the same value in the high/low registers.

But because of the RISC-V mentality of "everything is an extension", you can't do that, because then you wouldn't have the simpler "rotate" at all unless you had the full ternary extension.

At some point, the "RISC" part is just "UGLY".

Yes, x86 has both rotate and double shift, but at least there it's for legacy reasons, not because of a misguided "we want to intentionally fracture the ISA as much as possible, so that nobody can ever complain about the size of it".

I seriously believe that the whole mental model there is broken. It basically guarantees that there is not one RISC-V model, there are just lots of tiny fragments.

At some point the people involved should just admit that it causes more problems than it really solves.

Linus
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            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/03 02:25 AM
              The RISC-V bitmanip ISA extension has conditional movesWilco2019/11/03 06:38 AM
                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds2019/11/03 10:03 AM
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:29 AM
                  The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:38 AM
                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 07:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 09:36 AM
                            I'm glad you're not that blind :) (NT)none2019/11/04 09:36 AM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:23 AM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 06:16 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 11:42 PM
                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 06:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 06:04 PM
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                                    The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 03:31 AM
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                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 07:57 AM
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                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 04:07 PM
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                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 02:22 AM
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        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 07:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 08:12 AM
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