By: sylt (no.delete@this.thanks.com), November 3, 2019 1:35 pm
Room: Moderated Discussions
Ronald Maas (ronaldjmaas.delete@this.gmail.com) on November 3, 2019 7:58 am wrote:
> Wilco (wilco.dijkstra.delete@this.ntlworld.com) on November 2, 2019 11:20 am wrote:
> >
> > Yes I don't buy the fusion story either. It's not exactly trivial to fuse the 3 instructions
> > needed for a load with shifted index. Codesize will be better by adding encodings for
> > real instructions. And all but the highest-end implementations won't do any fusion,
> > while they would benefit the most from having powerful instructions.
> >
> > It's seems like they are still stuck in 80's RISC dogma. That video for example incorrectly assumes
> > micro-ops on AArch64 only ever write one register. Modern Arm cores process 4 registers per cycle
> > in a load-multiple or 2 load-pairs per cycle... It makes sense to design a new ISA to match expected
> > capabilities of future implementations, not religiously apply an ancient 2R/1W rule.
> >
> > Wilco
>
> On the very low end having a very basic ISA like RISC-V can be a real difference maker
> compared to other other ISAs, because it saves on die space where it counts.
>
> On high end implementations, the number of transistors needed for branch prediction, out of order
> execution, uncore, etc. will dwarf for what is needed to implement instruction fusion.
>
> So in my opinion RISC-V designers made the right call here.
>
> Ronald
>
As others have already pointed out, for the low end it's the other way around. For simple cores, you want to do as much as possible with as few instructions and complicated tricks as possible. A powerful ISA is very important. A few extra transistors for decoding and functional units is not important at all, its totally insignificant.
On the high end maybe you can afford the area for extra trickery to make up for the inferior ISA but that always comes at some cost and why would you want to start from behind adding complicated stuff just to catch up?
As Heikki said, RISC-V is too RISC (at least in its current form, maybe they can fix it with more extensions).
> Wilco (wilco.dijkstra.delete@this.ntlworld.com) on November 2, 2019 11:20 am wrote:
> >
> > Yes I don't buy the fusion story either. It's not exactly trivial to fuse the 3 instructions
> > needed for a load with shifted index. Codesize will be better by adding encodings for
> > real instructions. And all but the highest-end implementations won't do any fusion,
> > while they would benefit the most from having powerful instructions.
> >
> > It's seems like they are still stuck in 80's RISC dogma. That video for example incorrectly assumes
> > micro-ops on AArch64 only ever write one register. Modern Arm cores process 4 registers per cycle
> > in a load-multiple or 2 load-pairs per cycle... It makes sense to design a new ISA to match expected
> > capabilities of future implementations, not religiously apply an ancient 2R/1W rule.
> >
> > Wilco
>
> On the very low end having a very basic ISA like RISC-V can be a real difference maker
> compared to other other ISAs, because it saves on die space where it counts.
>
> On high end implementations, the number of transistors needed for branch prediction, out of order
> execution, uncore, etc. will dwarf for what is needed to implement instruction fusion.
>
> So in my opinion RISC-V designers made the right call here.
>
> Ronald
>
As others have already pointed out, for the low end it's the other way around. For simple cores, you want to do as much as possible with as few instructions and complicated tricks as possible. A powerful ISA is very important. A few extra transistors for decoding and functional units is not important at all, its totally insignificant.
On the high end maybe you can afford the area for extra trickery to make up for the inferior ISA but that always comes at some cost and why would you want to start from behind adding complicated stuff just to catch up?
As Heikki said, RISC-V is too RISC (at least in its current form, maybe they can fix it with more extensions).
