By: j (invalid.delete@this.example.net), November 4, 2019 12:30 am
Room: Moderated Discussions
anon (anon.delete@this.anon.com) on November 3, 2019 9:00 pm wrote:
> j (invalid.delete@this.example.net) on November 3, 2019 2:29 pm wrote:
> > Adrian (a.delete@this.acm.org) on November 2, 2019 9:33 am wrote:
> > > I refuse to believe to believe that instruction-pair fusion is simpler or better than the
> > > trivial enhancement of the instruction encoding to cover the more complex instructions that
> > > are needed in almost all loops, e.g. either with indexed or auto-indexed addressing.
> > >
> > >
> >
> > OTOH risc-v has compare-and-branch instructions so it doesn't need to fuse compare+jump,
> > nor does it have a flags register. At least the risc-v people are claiming that virtualizing
> > the flags register is a somewhat complex task for superscalar/OoO implementations.
>
> Do you mean renaming the flags register? Virtualizing it would generally
> be handled entirely by the hypervisor, no hardware required.
Sorry, poor wording on my part. I didn't mean anything related to hypervisors, virtual machines or the like. What I meant was whatever microarchitectural tricks which are needed to avoid bottle-necking performance on writing/reading the flags register.
AFAIK one common approach is to split up the flags register into several "virtual" registers (hence my use of the term "virtualizing") that can be handled separately. I don't know if they go all the way to having one such virtual register for each bit in the flags register, or if they are grouped.
Another might be to duplicate the flags, so that each normal register would have an associated flags register containing the flags for the latest instruction that wrote to that register, and then instructions that depend on the flag register such as jumps would somehow need to pick up a dependency on the correct flags register. Or maybe this is pointless if you just rename the flags as any normal register?
Anyway, however it's done, the claim by the RISC-V developers was that this is somewhat complex to do, and by not having a flags register RISC-V avoids that. Is it worth it? Don't know, maybe someone knows better?
> j (invalid.delete@this.example.net) on November 3, 2019 2:29 pm wrote:
> > Adrian (a.delete@this.acm.org) on November 2, 2019 9:33 am wrote:
> > > I refuse to believe to believe that instruction-pair fusion is simpler or better than the
> > > trivial enhancement of the instruction encoding to cover the more complex instructions that
> > > are needed in almost all loops, e.g. either with indexed or auto-indexed addressing.
> > >
> > >
> >
> > OTOH risc-v has compare-and-branch instructions so it doesn't need to fuse compare+jump,
> > nor does it have a flags register. At least the risc-v people are claiming that virtualizing
> > the flags register is a somewhat complex task for superscalar/OoO implementations.
>
> Do you mean renaming the flags register? Virtualizing it would generally
> be handled entirely by the hypervisor, no hardware required.
Sorry, poor wording on my part. I didn't mean anything related to hypervisors, virtual machines or the like. What I meant was whatever microarchitectural tricks which are needed to avoid bottle-necking performance on writing/reading the flags register.
AFAIK one common approach is to split up the flags register into several "virtual" registers (hence my use of the term "virtualizing") that can be handled separately. I don't know if they go all the way to having one such virtual register for each bit in the flags register, or if they are grouped.
Another might be to duplicate the flags, so that each normal register would have an associated flags register containing the flags for the latest instruction that wrote to that register, and then instructions that depend on the flag register such as jumps would somehow need to pick up a dependency on the correct flags register. Or maybe this is pointless if you just rename the flags as any normal register?
Anyway, however it's done, the claim by the RISC-V developers was that this is somewhat complex to do, and by not having a flags register RISC-V avoids that. Is it worth it? Don't know, maybe someone knows better?