RISC-V - incompetitive instruction set compared to ARMv8

By: Michael S (already5chosen.delete@this.yahoo.com), November 4, 2019 2:45 am
Room: Moderated Discussions
j (invalid.delete@this.example.net) on November 3, 2019 11:30 pm wrote:
> anon (anon.delete@this.anon.com) on November 3, 2019 9:00 pm wrote:
> > j (invalid.delete@this.example.net) on November 3, 2019 2:29 pm wrote:
> > > Adrian (a.delete@this.acm.org) on November 2, 2019 9:33 am wrote:
> > > > I refuse to believe to believe that instruction-pair fusion is simpler or better than the
> > > > trivial enhancement of the instruction encoding to cover the more complex instructions that
> > > > are needed in almost all loops, e.g. either with indexed or auto-indexed addressing.
> > > >
> > > >
> > >
> > > OTOH risc-v has compare-and-branch instructions so it doesn't need to fuse compare+jump,
> > > nor does it have a flags register. At least the risc-v people are claiming that virtualizing
> > > the flags register is a somewhat complex task for superscalar/OoO implementations.
> >
> > Do you mean renaming the flags register? Virtualizing it would generally
> > be handled entirely by the hypervisor, no hardware required.
>
> Sorry, poor wording on my part. I didn't mean anything related to hypervisors, virtual
> machines or the like. What I meant was whatever microarchitectural tricks which are
> needed to avoid bottle-necking performance on writing/reading the flags register.
>
> AFAIK one common approach is to split up the flags register into several "virtual" registers (hence
> my use of the term "virtualizing") that can be handled separately. I don't know if they go all the way
> to having one such virtual register for each bit in the flags register, or if they are grouped.
>
> Another might be to duplicate the flags, so that each normal register would have an associated flags register
> containing the flags for the latest instruction that wrote to that register, and then instructions that
> depend on the flag register such as jumps would somehow need to pick up a dependency on the correct flags
> register. Or maybe this is pointless if you just rename the flags as any normal register?
>


On x86 you do various tricks (Intel and AMD does not do it identically) because there are instructions that affect few arithmetic flags, but leave the rest of them unaffected. The prime example is INC/DEC that preserve carry flag, but modify the rest. So, if one handles flags as one register, INC/DEC become Partial Register Store.

You don't need it on newer ISAs, like aarch64, because ISA designers were aware of the problem and defined instruction sett in the way that any instruction either update all arithmetic flags or neither of them.

Another problem of x86 flags handling is shift instruction by variable count, which in case of count=zero has to preserve the flags. There is no Partial Register Store in this case, but there is still a dependency on old values of the flags, which in majority of cases (i.e. when count is non-zero) happens to be a false dependency.

Newer x86 processors support (as part of BMI2 extension) shifts that don't affect flags at all, but old instructions are still in very wide use, so implementer have to make them fast.


> Anyway, however it's done, the claim by the RISC-V developers was that this is somewhat complex to do, and
> by not having a flags register RISC-V avoids that. Is it worth it? Don't know, maybe someone knows better?
>

The only relatively significant field where absence of flags can cause problems is multiple-precision arithmetic. Not too significant for most of us. And it's not like absence of flags makes multiple-precision arithmetic many times slower at application level. Typically, the most cycles-consuming part of multiple-precision library is in house-keeping and other overheads, not in the arithmetic itself.
That's even more true in cryptographic applications of multiple-precision. For something, like full verification of ECDSA signature, effects of presence of absence of arithmetic flags in the ISA are barely above noise floor, esp. if one uses the most popular not too optimized implementation, i.e OSSL.

So, in that regard, I tend to think that RISC-V people are not too wrong,
I am much more concerned about conditional moves.



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TopicPosted ByDate
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    RISC-V - incompetitive instruction set compared to ARMv8Heikki Kultala2019/11/02 02:31 AM
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          RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/02 10:49 AM
            RISC-V - incompetitive instruction set compared to ARMv8Wilco2019/11/02 12:20 PM
              RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/02 01:57 PM
              RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas2019/11/03 08:58 AM
                RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/03 10:06 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 06:43 AM
                    RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/04 07:03 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 07:13 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 09:58 AM
                    RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 09:57 AM
                      RISC-V - incompetitive instruction set compared to ARMv8rwessel2019/11/04 10:25 AM
                        RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 10:48 AM
                RISC-V - incompetitive instruction set compared to ARMv8Wilco2019/11/03 12:09 PM
                  RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas2019/11/03 10:44 PM
                    RISC-V - incompetitive instruction set compared to ARMv8Wilco2019/11/04 04:01 PM
                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 04:14 PM
                      RISC-V - incompetitive instruction set compared to ARMv8R2019/11/04 11:35 PM
                RISC-V - incompetitive instruction set compared to ARMv8sylt2019/11/03 01:35 PM
                  RISC-V - incompetitive instruction set compared to ARMv8l2019/11/03 08:26 PM
            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/03 02:25 AM
              The RISC-V bitmanip ISA extension has conditional movesWilco2019/11/03 06:38 AM
                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds2019/11/03 10:03 AM
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:29 AM
                  The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:38 AM
                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 07:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 09:36 AM
                            I'm glad you're not that blind :) (NT)none2019/11/04 09:36 AM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:23 AM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 06:16 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 11:42 PM
                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 06:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 06:04 PM
                                  The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 02:21 AM
                                    The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 03:31 AM
                                    The RISC-V bitmanip ISA extension has conditional movesKonrad Schwarz2019/11/06 07:03 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 07:57 AM
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 08:55 AM
                      The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 07:24 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 04:07 PM
                          The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 05:02 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 11:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesnone2019/11/05 12:45 AM
                                RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas2019/11/05 05:41 PM
                                  RISC-V - incompetitive instruction set compared to ARMv8anonymou52019/11/06 12:24 AM
                                    The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/06 12:41 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 01:12 AM
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 02:22 AM
                                      The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 02:44 AM
                                        The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 02:50 AM
                                        The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 03:08 AM
                                          The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 07:24 AM
                                      The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 05:53 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnoko2019/11/06 11:07 AM
                                        The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 09:35 AM
                              The RISC-V bitmanip ISA extension has conditional movesj2019/11/05 01:43 AM
                          The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/04 05:39 PM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 06:25 PM
                      The RISC-V bitmanip ISA extension has conditional movesAnon2019/11/04 08:31 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Ronal2019/11/04 08:59 AM
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          RISC-V - incompetitive instruction set compared to ARMv8lockederboss2019/11/03 09:37 AM
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                RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 02:45 AM
                  RISC-V - incompetitive instruction set compared to ARMv8none2019/11/04 03:59 AM
                    RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/04 05:22 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Adrian2019/11/04 06:10 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 11:03 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/04 11:27 AM
                          RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 12:07 PM
                          RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 01:22 PM
                            RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/04 03:08 PM
                Flags RegisterDavid Hess2019/11/04 11:05 AM
                  Flags RegisterWilco2019/11/04 02:49 PM
                    Flags RegisterMaynard Handley2019/11/04 07:17 PM
                    Flags RegisterDavid Hess2019/11/05 04:35 PM
                      Flags RegisterWilco2019/11/05 05:54 PM
                        Flags RegisterMegol2019/11/06 06:11 AM
                          Flags RegisterMaynard Handley2019/11/07 02:42 PM
          RISC-V - instruction fusionAnon2019/11/06 06:40 PM
      RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 10:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 10:59 AM
          RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 11:11 AM
            RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 11:17 AM
              RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 11:54 AM
                RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/05 07:17 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/05 12:39 PM
                    RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/06 12:19 PM
                      RISC-V - incompetitive instruction set compared to ARMv8Doug S2019/11/06 12:47 PM
                        RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/06 07:36 PM
                          RISC-V - incompetitive instruction set compared to ARMv8Maynard Handley2019/11/06 08:32 PM
                            RISC-V - incompetitive instruction set compared to ARMv8j2019/11/07 04:33 AM
                          RISC-V - incompetitive instruction set compared to ARMv8TREZA2019/11/07 01:31 PM
                            RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/08 08:15 PM
                              RISC-V - incompetitive instruction set compared to ARMv8Maynard Handley2019/11/08 09:40 PM
                                RISC-V - incompetitive instruction set compared to ARMv8none2019/11/09 02:02 AM
                        RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/06 10:36 PM
                          The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 12:53 AM
                            Both are excellent ISAs ?Michael S2019/11/07 01:58 AM
                            The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/07 05:33 AM
                              The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 08:31 AM
                            The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/07 09:38 AM
                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 02:32 AM
                            The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 06:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/07 07:50 PM
                                The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 10:47 PM
                                  The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/08 03:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/08 06:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesDavid Hess2019/11/08 08:28 PM
                                      The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/08 09:14 PM
                      RISC-V - incompetitive instruction set compared to ARMv8G. Boniface2019/11/07 06:59 AM
                        Op fusion and superscalar execution do NOT share same hardwareHeikki Kultala2019/11/07 08:39 AM
                          Op fusion and superscalar execution do NOT share same hardwareRonald Maas2019/11/07 09:29 AM
                            Op fusion and superscalar execution do NOT share same hardwareanon2019/11/07 09:37 AM
                            Op fusion and superscalar execution do NOT share same hardwareWilco2019/11/07 12:41 PM
                            Op fusion and superscalar execution do NOT share same hardwareFoo_2019/11/07 12:42 PM
                              Op fusion and superscalar execution do NOT share same hardwareanon.12019/11/07 11:00 PM
                    RISC-V - incompetitive instruction set compared to ARMv8wumpus2019/11/06 05:19 PM
              RISC-V - conditional branches are problematic tooWilco2019/11/04 02:31 PM
                reg-reg branchesMichael S2019/11/06 02:37 AM
                  reg-reg branchesWilco2019/11/07 05:55 PM
      RISC-V - incompetitive instruction set compared to ARMv8Montaray Jack2019/11/08 02:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 07:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 08:12 AM
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