RISC-V - incompetitive instruction set compared to ARMv8

By: Ronal (ronaldjmaas.delete@this.gmail.com), November 4, 2019 7:59 am
Room: Moderated Discussions
Anon (Anon.delete@this.anon.com) on November 4, 2019 7:31 am wrote:
> Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on November 4, 2019 5:45 am wrote:
>
> > Because AArch64 is not a new ISA, it's an evolution of an older one. It also wasn't "a three
> > months project over the summer to design an ISA for academic use" done by a handful of people.
>
> 3 months to design a bad ISA is not a merit, I could design a bad ISA in a single day...
>
> But maybe this could explain somethings, like, how inexperienced they were to repeat so many mistakes.

Both 8086 and ARM ISA were designed by small teams with too little resources and time.
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Risc-V getting real?Anon2019/10/31 02:10 PM
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      Risc-V getting real?Gabriele Svelto2019/11/03 01:20 AM
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        Risc-V getting real?dmcq2019/11/04 05:41 AM
    Documentation QualityKonrad Schwarz2019/11/04 04:43 AM
      Documentation QualityGabriele Svelto2019/11/04 05:31 AM
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            RISC-V - incompetitive instruction set compared to ARMv8Wilco2019/11/02 11:20 AM
              RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/02 12:57 PM
              RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas2019/11/03 07:58 AM
                RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/03 09:06 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 05:43 AM
                    RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/04 06:03 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 06:13 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 08:58 AM
                    RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 08:57 AM
                      RISC-V - incompetitive instruction set compared to ARMv8rwessel2019/11/04 09:25 AM
                        RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 09:48 AM
                RISC-V - incompetitive instruction set compared to ARMv8Wilco2019/11/03 11:09 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas2019/11/03 09:44 PM
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                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 03:14 PM
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              The RISC-V bitmanip ISA extension has conditional movesWilco2019/11/03 05:38 AM
                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds2019/11/03 09:03 AM
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 05:29 AM
                  The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 05:38 AM
                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 05:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 05:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 08:36 AM
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                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 09:23 AM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 05:16 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:42 PM
                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 05:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 05:04 PM
                                  The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 01:21 AM
                                    The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 02:31 AM
                                    The RISC-V bitmanip ISA extension has conditional movesKonrad Schwarz2019/11/06 06:03 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 06:57 AM
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 07:55 AM
                      The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 06:24 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 03:07 PM
                          The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 04:02 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 11:45 PM
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                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 12:12 AM
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 01:22 AM
                                      The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 01:44 AM
                                        The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 01:50 AM
                                        The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 02:08 AM
                                          The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 06:24 AM
                                      The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 04:53 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnoko2019/11/06 10:07 AM
                                        The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 08:35 AM
                              The RISC-V bitmanip ISA extension has conditional movesj2019/11/05 12:43 AM
                          The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/04 04:39 PM
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                      RISC-V - incompetitive instruction set compared to ARMv8Adrian2019/11/04 05:10 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 10:03 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/04 10:27 AM
                          RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 11:07 AM
                          RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 12:22 PM
                            RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/04 02:08 PM
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        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 09:59 AM
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            RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 10:17 AM
              RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 10:54 AM
                RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/05 06:17 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/05 11:39 AM
                    RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/06 11:19 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Doug S2019/11/06 11:47 AM
                        RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/06 06:36 PM
                          RISC-V - incompetitive instruction set compared to ARMv8Maynard Handley2019/11/06 07:32 PM
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                          RISC-V - incompetitive instruction set compared to ARMv8TREZA2019/11/07 12:31 PM
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                              RISC-V - incompetitive instruction set compared to ARMv8Maynard Handley2019/11/08 08:40 PM
                                RISC-V - incompetitive instruction set compared to ARMv8none2019/11/09 01:02 AM
                        RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/06 09:36 PM
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                            The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/07 04:33 AM
                              The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 07:31 AM
                            The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/07 08:38 AM
                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 01:32 AM
                            The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 05:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/07 06:50 PM
                                The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 09:47 PM
                                  The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/08 02:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/08 05:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesDavid Hess2019/11/08 07:28 PM
                                      The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/08 08:14 PM
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                          Op fusion and superscalar execution do NOT share same hardwareRonald Maas2019/11/07 08:29 AM
                            Op fusion and superscalar execution do NOT share same hardwareanon2019/11/07 08:37 AM
                            Op fusion and superscalar execution do NOT share same hardwareWilco2019/11/07 11:41 AM
                            Op fusion and superscalar execution do NOT share same hardwareFoo_2019/11/07 11:42 AM
                              Op fusion and superscalar execution do NOT share same hardwareanon.12019/11/07 10:00 PM
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                reg-reg branchesMichael S2019/11/06 01:37 AM
                  reg-reg branchesWilco2019/11/07 04:55 PM
      RISC-V - incompetitive instruction set compared to ARMv8Montaray Jack2019/11/08 01:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 06:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 07:12 AM
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