By: Linus Torvalds (torvalds.delete@this.linux-foundation.org), November 4, 2019 11:27 am
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on November 4, 2019 10:03 am wrote:
>
> Doubling? That's way too optimistic.
> In most general case, one needs 5 RISC-V instruction to emulate add with carry.
What? No. I'm not a fan of how RISC-V has all those subsets, but add-with-carry isn't all that complex.
Afaik, a 128-bit add, which on x86 would be two instructions (add+adc), should only be four on RISC-V (add+sltu+add+add). No?
Is that optimal? No. But the doubling doesn't sound too optimistic in at least the obvious cases.
Would it have been more "interesting" to see architectures play with extra bits in the register instead (still honoring the 2R1W model), and maybe have a 66-bit register with C and O bits in the high bits? Yes it would have. But "interesting" tends to cause problems.
Not having a flags register wasn't a huge deal on alpha or MIPS. They had ninety nine problems, but lack of carry ain't one.
Linus
>
> Doubling? That's way too optimistic.
> In most general case, one needs 5 RISC-V instruction to emulate add with carry.
What? No. I'm not a fan of how RISC-V has all those subsets, but add-with-carry isn't all that complex.
Afaik, a 128-bit add, which on x86 would be two instructions (add+adc), should only be four on RISC-V (add+sltu+add+add). No?
Is that optimal? No. But the doubling doesn't sound too optimistic in at least the obvious cases.
Would it have been more "interesting" to see architectures play with extra bits in the register instead (still honoring the 2R1W model), and maybe have a 66-bit register with C and O bits in the high bits? Yes it would have. But "interesting" tends to cause problems.
Not having a flags register wasn't a huge deal on alpha or MIPS. They had ninety nine problems, but lack of carry ain't one.
Linus