By: David Hess (davidwhess.delete@this.gmail.com), November 4, 2019 12:07 pm
Room: Moderated Discussions
Linus Torvalds (torvalds.delete@this.linux-foundation.org) on November 4, 2019 10:27 am wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on November 4, 2019 10:03 am wrote:
> >
> > Doubling? That's way too optimistic.
> > In most general case, one needs 5 RISC-V instruction to emulate add with carry.
>
> What? No. I'm not a fan of how RISC-V has all those subsets, but add-with-carry isn't all that complex.
>
> Afaik, a 128-bit add, which on x86 would be two instructions (add+adc),
> should only be four on RISC-V (add+sltu+add+add). No?
>
> Is that optimal? No. But the doubling doesn't sound too optimistic in at least the obvious cases.
My notes say it required 4 times as many instructions and double the number of registers but the link I was given with examples of RISC-V code has been removed.
> Michael S (already5chosen.delete@this.yahoo.com) on November 4, 2019 10:03 am wrote:
> >
> > Doubling? That's way too optimistic.
> > In most general case, one needs 5 RISC-V instruction to emulate add with carry.
>
> What? No. I'm not a fan of how RISC-V has all those subsets, but add-with-carry isn't all that complex.
>
> Afaik, a 128-bit add, which on x86 would be two instructions (add+adc),
> should only be four on RISC-V (add+sltu+add+add). No?
>
> Is that optimal? No. But the doubling doesn't sound too optimistic in at least the obvious cases.
My notes say it required 4 times as many instructions and double the number of registers but the link I was given with examples of RISC-V code has been removed.
