RISC-V - conditional branches are problematic too

By: Wilco (wilco.dijkstra.delete@this.ntlworld.com), November 4, 2019 1:31 pm
Room: Moderated Discussions
Michael S (already5chosen.delete@this.yahoo.com) on November 4, 2019 10:17 am wrote:

> Then it should be about cmoves.
> RISC-V conditional branches are among the best in the industry.

I have to disagree there. The branch offsets are too small due to having 2 register fields in all conditional branches. There is no backup if the offset is too large - even unconditional branches have a significantly smaller range than any other ISA.

Register-immediate comparisons are the most common by far. The zero case is supported via the zero register, however it wastes at least 5 bits vs a dedicated branch-if-zero instruction (CBZ on AArch64 has a +-1MByte range vs +-4KB). Since comparisons with a non-zero immediate still require separate compare and branch instructions, having the reg-reg branch format isn't very useful, particularly if it is the only conditional branch format.

This shows there are very good reasons most ISAs settled on using condition codes. They require 9-10 bits less compared to reg-reg branch formats, enabling significantly larger branch offsets and less encoding space dedicated to conditional branches.

Wilco
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