The RISC-V bitmanip ISA extension has conditional moves

By: anon (spam.delete.delete@this.this.spam.com), November 4, 2019 5:02 pm
Room: Moderated Discussions
Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on November 4, 2019 3:07 pm wrote:
> anon (spam.delete.delete@this.this.spam.com) on November 4, 2019 6:24 am wrote:
> > How is that an excuse?
> > Why would I want a new ISA that insists on going through the same mistakes that everyone else
> > has outgrown 20 years ago? Is there some rule against learning from others' mistakes?
> >
> > Either way making excuses why it's not good doesn't make it any better even if they were valid.
> >
> > If RISC-V can reach the state AArch64 got today in 20 years instead
> > of 30 years that's great, but not exactly an argument for RISC-V.
> >
> >
> > RISC-V as many things before it succeeds on the back of cheaper mediocrity. It's cheaper than anything
> > else by virtue of being free and at least useable. That's essentially what happend with x86-64 and
> > most others as well. x64 is definitely not the cleanest or best 64 bit ISA out there, but it worked
> > and at the same performance those CPUs were the cheapest and that's all you need to win.
> >
> > So RISC-V being fast to market, starting as project with few resources and everything else you can come
> > up with are completely irrelevant to criticism about the ISA itself. Things could've objectively been done
> > better. You can not on one hand argue that RISC-V is getting done so fast and that's great but on the other
> > hand insist that they be allowed 10 years to fix their mistakes because that's just how ISAs work.
>
> I'm not making up any excuses. I was disproving Wilco's claim that ISAs are designed from a good clean base
> because that's simply untrue. ISAs are designed with an implementation and its constraints in mind that depend
> on its time of inception, the applications it will be targeted to and the resources available.
>
> Picking AArch64 in a comparison with the base RISC-V ISA is meaningless
> because the constraints and goals of both were very different.
>

Was one of the constraints for RISC-V that it can't be designed from a good clean base?

> The original ARM ISA was designed with a set of constraints that made odd choices like 26-bit pointers or
> the ability to use the PC as an arbitrary GP register meaningful. Those constraints made no sense in the
> context of AArch64 which was designed for high-performance applications over two decades later. In turn
> AArch64 sucks big time if your target is a microcontroller, does that make it a bad ISA? There is no such
> thing as a "better" ISA unless you also specify the implementation constraints and design targets.
>

What is your point? That RISC-V is perfect? That RISC-V can't be compared with AArch64 because AArch64 lacks odd choices? Where are you going with this?

> RISC-V was designed with the goal of having a commercially and legally unencumbered ISA that could be implemented
> by a bunch of undergrads with no previous VLSI design experience and limited access to the tools required for
> the job. In that context choices such as single-cycle execution of all instructions and strict 2R1W access
> made perfect sense; the implementation would be dead simple. And indeed it was successful at that. Quite a
> lot more successful than any other non-commercial ISA out there, and there's been quite a few of them if you've
> been paying attention. And quite a lot more successful than what most people thought, after all ARM felt the
> need to launch a smear campaign against RISC-V last year. How's that for an inferior ISA?

Have you succesfully skipped the paragraph where I wrote about commercial success not being an indicator of an ISA's quality?

Ah yes, the original RISC was perfect and how dare anyone suggest otherwise. Nevermind that when using RISC-V for something other than toy projects the context changes and it doesn't not make perfect sense anymore. It's a bit schizophrenic. Pushing for RISC-V as an alternative to commercial ISAs but hiding behind the "it's just an academic tool" excuse whenever someone dares to suggest that the choices that were made are not ideal for that.

Of course the quality of marketing material is a direct indicator of ISA quality.
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        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 07:03 AM
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