The RISC-V bitmanip ISA extension has conditional moves

By: Maynard Handley (name99.delete@this.name99.org), November 4, 2019 6:16 pm
Room: Moderated Discussions
Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on November 4, 2019 6:17 am wrote:
> none (none.delete@this.none.com) on November 4, 2019 5:55 am wrote:
> > Come on you're more knowledgeable than that. You can tell that of Thumb2 vs ARM. AArch64
> > is as much an evolution of ARM as RISC-V is an evolution of MIPS.
>
> If you push that far enough all ISAs are related and we can go home. That doesn't change
> the fact that the people who designed AArch64 were the same people and the same company
> that designed all the previous iterations of the ARM ISA and they did so with the goal
> of having mixed 32/64-bit implementations. That's not true of RISC-V and MIPS.
>
> > Sorry but being a three-month project does not excuse the state of RISC-V. Quite the
> > contrary.
>
> So the base ISA designed by a large company with the support of other large companies is better
> than one that has been hacked together in three months in academia? Color me surprised.

I'm not sure what your point is, Gabriel.
I'm sure there are a few other viewpoints here, but for most of us this is not an issue of morality, or patting little heads, or anything along those lines, it's a matter of engineering. Some may or may not find it interesting what ARMv1 looked like 30 years ago, or how many people put together RISC-V, but those are UTTERLY IRRELEVANT to the interests of most of us.

Again there are differences, and some among us are very interested in the state of the embedded market; but most of us care more about larger cores -- mobile through server. Even if RISC-V were superbly designed for lightweight embedded, that's uninteresting to someone whose primary concern is the extent to which it forms a promising basis (firstly as an ISA, secondly as a community) for joining the big boys of Apple, Intel and AMD, or at the very least the middle-weight cores of ARM's high end.

Think of it as _The Voice_ ISA edition. Back-story, pretty looks, demographics, don't matter to the judges; only one thing does --- the sound we hear.
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              The RISC-V bitmanip ISA extension has conditional movesWilco2019/11/03 06:38 AM
                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds2019/11/03 10:03 AM
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:29 AM
                  The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:38 AM
                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 07:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 09:36 AM
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                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:23 AM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 06:16 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 11:42 PM
                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 06:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 06:04 PM
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                            The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/07 05:33 AM
                              The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 08:31 AM
                            The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/07 09:38 AM
                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 02:32 AM
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        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 07:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 08:12 AM
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