The RISC-V bitmanip ISA extension has conditional moves

By: Maynard Handley (name99.delete@this.name99.org), November 4, 2019 5:25 pm
Room: Moderated Discussions
Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on November 4, 2019 3:07 pm wrote:
> anon (spam.delete.delete@this.this.spam.com) on November 4, 2019 6:24 am wrote:
> > How is that an excuse?
> > Why would I want a new ISA that insists on going through the same mistakes that everyone else
> > has outgrown 20 years ago? Is there some rule against learning from others' mistakes?
> >
> > Either way making excuses why it's not good doesn't make it any better even if they were valid.
> >
> > If RISC-V can reach the state AArch64 got today in 20 years instead
> > of 30 years that's great, but not exactly an argument for RISC-V.
> >
> >
> > RISC-V as many things before it succeeds on the back of cheaper mediocrity. It's cheaper than anything
> > else by virtue of being free and at least useable. That's essentially what happend with x86-64 and
> > most others as well. x64 is definitely not the cleanest or best 64 bit ISA out there, but it worked
> > and at the same performance those CPUs were the cheapest and that's all you need to win.
> >
> > So RISC-V being fast to market, starting as project with few resources and everything else you can come
> > up with are completely irrelevant to criticism about the ISA itself. Things could've objectively been done
> > better. You can not on one hand argue that RISC-V is getting done so fast and that's great but on the other
> > hand insist that they be allowed 10 years to fix their mistakes because that's just how ISAs work.
>
> I'm not making up any excuses. I was disproving Wilco's claim that ISAs are designed from a good clean base
> because that's simply untrue. ISAs are designed with an implementation and its constraints in mind that depend
> on its time of inception, the applications it will be targeted to and the resources available.
>
> Picking AArch64 in a comparison with the base RISC-V ISA is meaningless
> because the constraints and goals of both were very different.
>
> The original ARM ISA was designed with a set of constraints that made odd choices like 26-bit pointers or
> the ability to use the PC as an arbitrary GP register meaningful. Those constraints made no sense in the
> context of AArch64 which was designed for high-performance applications over two decades later. In turn
> AArch64 sucks big time if your target is a microcontroller, does that make it a bad ISA? There is no such
> thing as a "better" ISA unless you also specify the implementation constraints and design targets.
>
> RISC-V was designed with the goal of having a commercially and legally unencumbered ISA that could be implemented
> by a bunch of undergrads with no previous VLSI design experience and limited access to the tools required for
> the job.

If THAT is what you consider the metric of success (ie RISC-V is a better "commercially and legally unencumbered ISA that can be implemented ...") then sure, RISC-V is a great success.
But remember that that's a metric of little interest to most of us.
You keep saying things like RISC-V is most successful, is great success, ...; but what seems to interest you as the success metric matters little to most of us.
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TopicPosted ByDate
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                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 06:13 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 08:58 AM
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            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/03 01:25 AM
              The RISC-V bitmanip ISA extension has conditional movesWilco2019/11/03 05:38 AM
                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds2019/11/03 09:03 AM
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 05:29 AM
                  The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 05:38 AM
                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 05:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 05:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 08:36 AM
                            I'm glad you're not that blind :) (NT)none2019/11/04 08:36 AM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 09:23 AM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 05:16 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:42 PM
                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 05:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 05:04 PM
                                  The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 01:21 AM
                                    The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 02:31 AM
                                    The RISC-V bitmanip ISA extension has conditional movesKonrad Schwarz2019/11/06 06:03 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 06:57 AM
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 07:55 AM
                      The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 06:24 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 03:07 PM
                          The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 04:02 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:39 PM
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                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 01:22 AM
                                      The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 01:44 AM
                                        The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 01:50 AM
                                        The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 02:08 AM
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                                      The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 04:53 AM
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                                        The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 08:35 AM
                              The RISC-V bitmanip ISA extension has conditional movesj2019/11/05 12:43 AM
                          The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/04 04:39 PM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 05:25 PM
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                          The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/06 11:53 PM
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                            The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/07 04:33 AM
                              The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 07:31 AM
                            The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/07 08:38 AM
                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 01:32 AM
                            The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 05:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/07 06:50 PM
                                The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 09:47 PM
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                                    The RISC-V bitmanip ISA extension has conditional movesDavid Hess2019/11/08 07:28 PM
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                        Op fusion and superscalar execution do NOT share same hardwareHeikki Kultala2019/11/07 07:39 AM
                          Op fusion and superscalar execution do NOT share same hardwareRonald Maas2019/11/07 08:29 AM
                            Op fusion and superscalar execution do NOT share same hardwareanon2019/11/07 08:37 AM
                            Op fusion and superscalar execution do NOT share same hardwareWilco2019/11/07 11:41 AM
                            Op fusion and superscalar execution do NOT share same hardwareFoo_2019/11/07 11:42 AM
                              Op fusion and superscalar execution do NOT share same hardwareanon.12019/11/07 10:00 PM
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                reg-reg branchesMichael S2019/11/06 01:37 AM
                  reg-reg branchesWilco2019/11/07 04:55 PM
      RISC-V - incompetitive instruction set compared to ARMv8Montaray Jack2019/11/08 01:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 06:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 07:12 AM
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