The RISC-V bitmanip ISA extension has conditional moves

By: Gabriele Svelto (gabriele.svelto.delete@this.gmail.com), November 4, 2019 10:39 pm
Room: Moderated Discussions
anon (spam.delete.delete@this.this.spam.com) on November 4, 2019 4:02 pm wrote:
> Was one of the constraints for RISC-V that it can't be designed from a good clean base?

I stated what the constraints where, do you challenge that? Do you challenge the fact that ISAs are not designed that way? If you consider something like AArch64 "a good clean base" then the RISC-V Rocket core would never have been realized because it would have been far too complex.

> What is your point? That RISC-V is perfect? That RISC-V can't be compared with
> AArch64 because AArch64 lacks odd choices? Where are you going with this?

My point is that ISA are not born like Wilco described, as if they were designed in a vacumm to make them "clean" or "good". I was damn clear about it and mentioned nothing about perfection. They're designed to fit a series of design constraints which are dictated by their first implementation, their goals and the resources available for it. Do you dispute this? Go back and read my original reply to Wilco if you missed it, I spelled it quite clearly.

> Have you succesfully skipped the paragraph where I wrote about
> commercial success not being an indicator of an ISA's quality?
>
> Ah yes, the original RISC was perfect and how dare anyone suggest otherwise. Nevermind that
> when using RISC-V for something other than toy projects the context changes and it doesn't
> not make perfect sense anymore. It's a bit schizophrenic. Pushing for RISC-V as an alternative
> to commercial ISAs but hiding behind the "it's just an academic tool" excuse whenever someone
> dares to suggest that the choices that were made are not ideal for that.

I pointed out in several posts that commercial implementations of RISC-V are using significant extensions that deviate from the base instruction set. I provided ample external references to that and made no claim about perfection of the ISA or otherwise. You and others brought up the comparison between AArch64 and base, unmodified RISC-V and I pointed out why that comparison was flawed and meaningless. Don't try to put words in my mouth or dodge my argument because that doesn't work with me.

If you want to compare RISC-V to other ISAs then do so in an appropriate context. For example, how does the RISC-V extension shipped in something like the N22 core stack up with a comparable Cortex Mx core?
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Risc-V getting real?Anon2019/10/31 02:10 PM
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                RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/03 09:06 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 05:43 AM
                    RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/04 06:03 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 06:13 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 08:58 AM
                    RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 08:57 AM
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                        RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 09:48 AM
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            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/03 01:25 AM
              The RISC-V bitmanip ISA extension has conditional movesWilco2019/11/03 05:38 AM
                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds2019/11/03 09:03 AM
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 05:29 AM
                  The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 05:38 AM
                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 05:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 05:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 08:36 AM
                            I'm glad you're not that blind :) (NT)none2019/11/04 08:36 AM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 09:23 AM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 05:16 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:42 PM
                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 05:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 05:04 PM
                                  The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 01:21 AM
                                    The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 02:31 AM
                                    The RISC-V bitmanip ISA extension has conditional movesKonrad Schwarz2019/11/06 06:03 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 06:57 AM
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 07:55 AM
                      The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 06:24 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 03:07 PM
                          The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 04:02 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 11:45 PM
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                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 12:12 AM
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 01:22 AM
                                      The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 01:44 AM
                                        The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 01:50 AM
                                        The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 02:08 AM
                                          The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 06:24 AM
                                      The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 04:53 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnoko2019/11/06 10:07 AM
                                        The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 08:35 AM
                              The RISC-V bitmanip ISA extension has conditional movesj2019/11/05 12:43 AM
                          The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/04 04:39 PM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 05:25 PM
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                          RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 11:07 AM
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            RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 10:17 AM
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                RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/05 06:17 AM
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                          The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/06 11:53 PM
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                            The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/07 04:33 AM
                              The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 07:31 AM
                            The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/07 08:38 AM
                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 01:32 AM
                            The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 05:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/07 06:50 PM
                                The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 09:47 PM
                                  The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/08 02:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/08 05:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesDavid Hess2019/11/08 07:28 PM
                                      The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/08 08:14 PM
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                        Op fusion and superscalar execution do NOT share same hardwareHeikki Kultala2019/11/07 07:39 AM
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                            Op fusion and superscalar execution do NOT share same hardwareanon2019/11/07 08:37 AM
                            Op fusion and superscalar execution do NOT share same hardwareWilco2019/11/07 11:41 AM
                            Op fusion and superscalar execution do NOT share same hardwareFoo_2019/11/07 11:42 AM
                              Op fusion and superscalar execution do NOT share same hardwareanon.12019/11/07 10:00 PM
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                reg-reg branchesMichael S2019/11/06 01:37 AM
                  reg-reg branchesWilco2019/11/07 04:55 PM
      RISC-V - incompetitive instruction set compared to ARMv8Montaray Jack2019/11/08 01:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 06:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 07:12 AM
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