The RISC-V bitmanip ISA extension has conditional moves

By: Gabriele Svelto (gabriele.svelto.delete@this.gmail.com), November 4, 2019 11:42 pm
Room: Moderated Discussions
Maynard Handley (name99.delete@this.name99.org) on November 4, 2019 5:16 pm wrote:
> I'm not sure what your point is, Gabriel.
> I'm sure there are a few other viewpoints here, but for most of us this is not an issue of morality,
> or patting little heads, or anything along those lines, it's a matter of engineering. Some may
> or may not find it interesting what ARMv1 looked like 30 years ago, or how many people put together
> RISC-V, but those are UTTERLY IRRELEVANT to the interests of most of us.
>
> Again there are differences, and some among us are very interested in the state of the embedded market;
> but most of us care more about larger cores -- mobile through server. Even if RISC-V were superbly
> designed for lightweight embedded, that's uninteresting to someone whose primary concern is the extent
> to which it forms a promising basis (firstly as an ISA, secondly as a community) for joining the big
> boys of Apple, Intel and AMD, or at the very least the middle-weight cores of ARM's high end.
>
> Think of it as _The Voice_ ISA edition. Back-story, pretty looks, demographics,
> don't matter to the judges; only one thing does --- the sound we hear.

Sorry that my posts are not interesting to you. Here's one thing though: if you're interested only in larger cores "mobile through server" in your words then you'll have to wait for a RISC-V implementation that target that markets if you want to make an ISA comparison. I'm sure that particular implementation will have an ISA that will be significantly different than base, vanilla RISC-V just like modern ARM cores ships with ISAs very different from the original ones.

In the meantime comparing AArch64 to base RISC-V and claiming superiority of the latter is as meaningless as comparing it to the original ARM.
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            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/03 02:25 AM
              The RISC-V bitmanip ISA extension has conditional movesWilco2019/11/03 06:38 AM
                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds2019/11/03 10:03 AM
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:29 AM
                  The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:38 AM
                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 07:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 09:36 AM
                            I'm glad you're not that blind :) (NT)none2019/11/04 09:36 AM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:23 AM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 06:16 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 11:42 PM
                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 06:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 06:04 PM
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                                    The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 03:31 AM
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                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 02:22 AM
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        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 07:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 08:12 AM
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