By: none (none.delete@this.none.com), November 5, 2019 12:45 am
Room: Moderated Discussions
Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on November 4, 2019 10:39 pm wrote:
[...]
> I pointed out in several posts that commercial implementations of RISC-V are using significant extensions
> that deviate from the base instruction set.
This can quickly get out of control. I remember the mess MIPS was. Everyone had their own
extensions which required their own tools, which obviously quickly rotted (e.g. the R5900
found in PS2).
It's already messy on x86 and AArch64 with the plethora of extensions but at least all
these extensions are controlled by a central body. I hope RISC-V companies won't play a
game of specific extensions and stick to Standard Extensions for not deeply embedded cores.
[...]
> I pointed out in several posts that commercial implementations of RISC-V are using significant extensions
> that deviate from the base instruction set.
This can quickly get out of control. I remember the mess MIPS was. Everyone had their own
extensions which required their own tools, which obviously quickly rotted (e.g. the R5900
found in PS2).
It's already messy on x86 and AArch64 with the plethora of extensions but at least all
these extensions are controlled by a central body. I hope RISC-V companies won't play a
game of specific extensions and stick to Standard Extensions for not deeply embedded cores.