RISC-V - incompetitive instruction set compared to ARMv8

By: anon.1 (abc.delete@this.def.com), November 5, 2019 7:17 am
Room: Moderated Discussions
David Hess (davidwhess.delete@this.gmail.com) on November 4, 2019 10:54 am wrote:
> Michael S (already5chosen.delete@this.yahoo.com) on November 4, 2019 10:17 am wrote:
> > David Hess (davidwhess.delete@this.gmail.com) on November 4, 2019 10:11 am wrote:
> > > Michael S (already5chosen.delete@this.yahoo.com) on November 4, 2019 9:59 am wrote:
> > > >
> > > > Do you mean "lack of conditional move" ?
> > >
> > > It has been a while so it might have been. What I remember is lack of support for "conditionals"
> > > leading to documentation showing how they are implemented with multi-instruction sequences.
> >
> > Then it should be about cmoves.
> > RISC-V conditional branches are among the best in the industry.
>
> I managed to find the forum discussion and it was ultimately about support for multiword
> math with no flag state being preserved. Unfortunately the link to the RISC-V documentation
> was apparently removed so the discussion is useless now.
>

Somewhat orthogonal: I don't understand the opposition to 2 reg source loads though. It still satisfies 2R1W.
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