Adrian (a.delete@this.acm.org) on November 5, 2019 5:25 am wrote:
> Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on November 4, 2019 10:42 pm wrote:
> >
> > Sorry that my posts are not interesting to you. Here's one thing though: if you're interested
> > only in larger cores "mobile through server" in your words then you'll have to wait for a RISC-V
> > implementation that target that markets if you want to make an ISA comparison. I'm sure that particular
> > implementation will have an ISA that will be significantly different than base, vanilla RISC-V
> > just like modern ARM cores ships with ISAs very different from the original ones.
> >
> > In the meantime comparing AArch64 to base RISC-V and claiming superiority
> > of the latter is as meaningless as comparing it to the original ARM.
>
>
>
> I agree that the initial products with RISC-V target a very different
> market, so their base ISA might not be comparable with AArch64.
>
>
> Nevertheless I believe that everybody who referred to AArch64 did that not as an example of an ISA targeting
> the same market, but as an example of an ISA which was designed recently so that it could take into
> account the experience with the older RISC ISAs in order to attempt to have a superior ISA.
>
>
> What I do not like about RISC-V is that I have not seen in the base ISA any sign that
> its designers understood what was good and what was bad in the older RISC or CISC ISAs.
> On the other hand, I appreciated very much the propaganda that the RISC-V team made
> in favor of vector extensions, about which their opinions were all right.
>
>
> If we refer to the same market, then RISC-V sucks badly in comparison with ARMv7-M & ARMv6-M, despite
> the fact that those were partially constrained by backwards compatibility with an ancient ISA, as
> shown e.g. in the cryptography paper that was linked in one of the messages from this thread.
>
>
>
Well at least RISC-V consciously avoided a bunch of pitfalls such as:
- register windows
- branch delay slot
- let implementation details influence the ISA, such as ARM 32-bit PC offset of 8 bytes

Now time will tell if extensions are a great idea or a train wreck waiting to happen. My biggest concern is if you have 10s of different extensions defined, there are potentially millions of different implementations possible that support a slightly different mix of extensions. For Linux all the major distros aligned on RV64GC as a baseline which I think is a good thing. I am curious to see how future extensions like packed SIMD or vector are going to be handled after they become finalized.

Ronald