Real World Technologies - Forums - Thread: Risc-V getting real?

By: Ronald Maas (ronaldjmaas.delete@this.gmail.com), November 5, 2019 11:41 pm

anonymou5 (no.delete@this.spam.com) on November 5, 2019 11:24 pm wrote:
> > RISC-V Foundation governs the official extensions. So not
> > much difference compared how Intel / AMD / ARM governs
> > their ISA extensions. Except you have an option to contribute and influence the process with RISC-V.
>
> Your "Except..." comment makes it sound as if Intel, AMD, and ARM aren't taking ISA input.
>
> They actually do. From what they consider relevant customers. But also from individuals.

I know Microsoft and some other organizations had a big influence on the definition of AMD64. Do you know any examples where that happened? Especially interested in contributions done by individuals?

Ronald

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Topic	Posted By	Date
Risc-V getting real?	Anon	2019/10/31 02:10 PM
Risc-V getting real?	Gabriele Svelto	2019/11/01 02:28 AM
Risc-V getting real?	anon	2019/11/02 12:46 AM
Risc-V getting real?	lockederboss	2019/11/02 12:49 AM
Risc-V getting real?	Gabriele Svelto	2019/11/03 01:20 AM
Risc-V getting real?	Michael S	2019/11/03 02:03 AM
Risc-V getting real?	Gabriele Svelto	2019/11/03 03:45 AM
Risc-V getting real?	anon	2019/11/03 07:29 PM
Risc-V getting real?	Gabriele Svelto	2019/11/04 05:39 AM
Risc-V getting real?	dmcq	2019/11/04 05:41 AM
Documentation Quality	Konrad Schwarz	2019/11/04 04:43 AM
Documentation Quality	Gabriele Svelto	2019/11/04 05:31 AM
Documentation Quality	Anon	2019/11/04 11:28 AM
Trivium: Andy Glew works for SiFive	Paul A. Clayton	2019/11/01 09:51 AM
RISC-V - incompetitive instruction set compared to ARMv8	Heikki Kultala	2019/11/02 01:31 AM
RISC-V - incompetitive instruction set compared to ARMv8	Ronald Maas	2019/11/02 09:02 AM
RISC-V - incompetitive instruction set compared to ARMv8	Ronald Maas	2019/11/02 09:04 AM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/02 02:18 PM
RISC-V - incompetitive instruction set compared to ARMv8	Adrian	2019/11/02 09:33 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/02 09:49 AM
RISC-V - incompetitive instruction set compared to ARMv8	Wilco	2019/11/02 11:20 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/02 12:57 PM
RISC-V - incompetitive instruction set compared to ARMv8	Ronald Maas	2019/11/03 07:58 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/03 09:06 AM
RISC-V - incompetitive instruction set compared to ARMv8	Gabriele Svelto	2019/11/04 05:43 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/04 06:03 AM
RISC-V - incompetitive instruction set compared to ARMv8	Gabriele Svelto	2019/11/04 06:13 AM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 08:58 AM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 08:57 AM
RISC-V - incompetitive instruction set compared to ARMv8	rwessel	2019/11/04 09:25 AM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 09:48 AM
RISC-V - incompetitive instruction set compared to ARMv8	Wilco	2019/11/03 11:09 AM
RISC-V - incompetitive instruction set compared to ARMv8	Ronald Maas	2019/11/03 09:44 PM
RISC-V - incompetitive instruction set compared to ARMv8	Wilco	2019/11/04 03:01 PM
RISC-V - incompetitive instruction set compared to ARMv8	Gabriele Svelto	2019/11/04 03:14 PM
RISC-V - incompetitive instruction set compared to ARMv8	R	2019/11/04 10:35 PM
RISC-V - incompetitive instruction set compared to ARMv8	sylt	2019/11/03 12:35 PM
RISC-V - incompetitive instruction set compared to ARMv8	l	2019/11/03 07:26 PM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/03 01:25 AM
The RISC-V bitmanip ISA extension has conditional moves	Wilco	2019/11/03 05:38 AM
The RISC-V bitmanip ISA extension has conditional moves	Linus Torvalds	2019/11/03 09:03 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 05:29 AM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/04 05:38 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 05:45 AM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/04 05:55 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 06:17 AM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/04 08:36 AM
I'm glad you're not that blind :) (NT)	none	2019/11/04 08:36 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 09:23 AM
The RISC-V bitmanip ISA extension has conditional moves	Maynard Handley	2019/11/04 05:16 PM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 10:42 PM
The RISC-V bitmanip ISA extension has conditional moves	Adrian	2019/11/05 05:25 AM
The RISC-V bitmanip ISA extension has conditional moves	Ronald Maas	2019/11/05 05:04 PM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/06 01:21 AM
The RISC-V bitmanip ISA extension has conditional moves	dmcq	2019/11/06 02:31 AM
The RISC-V bitmanip ISA extension has conditional moves	Konrad Schwarz	2019/11/06 06:03 AM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/06 06:57 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/06 07:55 AM
The RISC-V bitmanip ISA extension has conditional moves	anon	2019/11/04 06:24 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 03:07 PM
The RISC-V bitmanip ISA extension has conditional moves	anon	2019/11/04 04:02 PM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 10:39 PM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/04 11:45 PM
RISC-V - incompetitive instruction set compared to ARMv8	Ronald Maas	2019/11/05 04:41 PM
RISC-V - incompetitive instruction set compared to ARMv8	anonymou5	2019/11/05 11:24 PM
The RISC-V bitmanip ISA extension has conditional moves	Ronald Maas	2019/11/05 11:41 PM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/06 12:12 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/06 01:22 AM
The RISC-V bitmanip ISA extension has conditional moves	Adrian	2019/11/06 01:44 AM
The RISC-V bitmanip ISA extension has conditional moves	Adrian	2019/11/06 01:50 AM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/06 02:08 AM
The RISC-V bitmanip ISA extension has conditional moves	Adrian	2019/11/06 06:24 AM
The RISC-V bitmanip ISA extension has conditional moves	dmcq	2019/11/06 04:53 AM
The RISC-V bitmanip ISA extension has conditional moves	noko	2019/11/06 10:07 AM
The RISC-V bitmanip ISA extension has conditional moves	Ronald Maas	2019/11/07 08:35 AM
The RISC-V bitmanip ISA extension has conditional moves	j	2019/11/05 12:43 AM
The RISC-V bitmanip ISA extension has conditional moves	dmcq	2019/11/04 04:39 PM
The RISC-V bitmanip ISA extension has conditional moves	Maynard Handley	2019/11/04 05:25 PM
The RISC-V bitmanip ISA extension has conditional moves	Anon	2019/11/04 07:31 AM
RISC-V - incompetitive instruction set compared to ARMv8	Ronal	2019/11/04 07:59 AM
RISC-V - incompetitive instruction set compared to ARMv8	dmcq	2019/11/02 02:00 PM
RISC-V - incompetitive instruction set compared to ARMv8	lockederboss	2019/11/03 08:37 AM
RISC-V - incompetitive instruction set compared to ARMv8	j	2019/11/03 02:29 PM
RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/03 09:00 PM
RISC-V - incompetitive instruction set compared to ARMv8	j	2019/11/03 11:30 PM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 01:45 AM
RISC-V - incompetitive instruction set compared to ARMv8	none	2019/11/04 02:59 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/04 04:22 AM
RISC-V - incompetitive instruction set compared to ARMv8	Adrian	2019/11/04 05:10 AM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 10:03 AM
RISC-V - incompetitive instruction set compared to ARMv8	Linus Torvalds	2019/11/04 10:27 AM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 11:07 AM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 12:22 PM
RISC-V - incompetitive instruction set compared to ARMv8	Linus Torvalds	2019/11/04 02:08 PM
Flags Register	David Hess	2019/11/04 10:05 AM
Flags Register	Wilco	2019/11/04 01:49 PM
Flags Register	Maynard Handley	2019/11/04 06:17 PM
Flags Register	David Hess	2019/11/05 03:35 PM
Flags Register	Wilco	2019/11/05 04:54 PM
Flags Register	Megol	2019/11/06 05:11 AM
Flags Register	Maynard Handley	2019/11/07 01:42 PM
RISC-V - instruction fusion	Anon	2019/11/06 05:40 PM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 09:38 AM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 09:59 AM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 10:11 AM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 10:17 AM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 10:54 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon.1	2019/11/05 06:17 AM
RISC-V - incompetitive instruction set compared to ARMv8	Linus Torvalds	2019/11/05 11:39 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon.1	2019/11/06 11:19 AM
RISC-V - incompetitive instruction set compared to ARMv8	Doug S	2019/11/06 11:47 AM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/06 06:36 PM
RISC-V - incompetitive instruction set compared to ARMv8	Maynard Handley	2019/11/06 07:32 PM
RISC-V - incompetitive instruction set compared to ARMv8	j	2019/11/07 03:33 AM
RISC-V - incompetitive instruction set compared to ARMv8	TREZA	2019/11/07 12:31 PM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/08 07:15 PM
RISC-V - incompetitive instruction set compared to ARMv8	Maynard Handley	2019/11/08 08:40 PM
RISC-V - incompetitive instruction set compared to ARMv8	none	2019/11/09 01:02 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon.1	2019/11/06 09:36 PM
The RISC-V bitmanip ISA extension has conditional moves	Ronald Maas	2019/11/06 11:53 PM
Both are excellent ISAs ?	Michael S	2019/11/07 12:58 AM
The RISC-V bitmanip ISA extension has conditional moves	dmcq	2019/11/07 04:33 AM
The RISC-V bitmanip ISA extension has conditional moves	Ronald Maas	2019/11/07 07:31 AM
The RISC-V bitmanip ISA extension has conditional moves	Adrian	2019/11/07 08:38 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/08 01:32 AM
The RISC-V bitmanip ISA extension has conditional moves	anon.1	2019/11/07 05:39 PM
The RISC-V bitmanip ISA extension has conditional moves	Brett	2019/11/07 06:50 PM
The RISC-V bitmanip ISA extension has conditional moves	anon.1	2019/11/07 09:47 PM
The RISC-V bitmanip ISA extension has conditional moves	Brett	2019/11/08 02:00 PM
The RISC-V bitmanip ISA extension has conditional moves	Maynard Handley	2019/11/08 05:00 PM
The RISC-V bitmanip ISA extension has conditional moves	David Hess	2019/11/08 07:28 PM
The RISC-V bitmanip ISA extension has conditional moves	anon.1	2019/11/08 08:14 PM
RISC-V - incompetitive instruction set compared to ARMv8	G. Boniface	2019/11/07 05:59 AM
Op fusion and superscalar execution do NOT share same hardware	Heikki Kultala	2019/11/07 07:39 AM
Op fusion and superscalar execution do NOT share same hardware	Ronald Maas	2019/11/07 08:29 AM
Op fusion and superscalar execution do NOT share same hardware	anon	2019/11/07 08:37 AM
Op fusion and superscalar execution do NOT share same hardware	Wilco	2019/11/07 11:41 AM
Op fusion and superscalar execution do NOT share same hardware	Foo_	2019/11/07 11:42 AM
Op fusion and superscalar execution do NOT share same hardware	anon.1	2019/11/07 10:00 PM
RISC-V - incompetitive instruction set compared to ARMv8	wumpus	2019/11/06 04:19 PM
RISC-V - conditional branches are problematic too	Wilco	2019/11/04 01:31 PM
reg-reg branches	Michael S	2019/11/06 01:37 AM
reg-reg branches	Wilco	2019/11/07 04:55 PM
RISC-V - incompetitive instruction set compared to ARMv8	Montaray Jack	2019/11/08 01:38 AM
RISC-V - incompetitive instruction set compared to ARMv8	Gabriele Svelto	2019/11/08 06:03 AM
Risc-V getting real?	Konrad Schwarz	2019/11/20 07:12 AM

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Body:	No Text Ronald Maas (ronaldjmaas.delete@this.gmail.com) on November 5, 2019 11:41 pm wrote: > anonymou5 (no.delete@this.spam.com) on November 5, 2019 11:24 pm wrote: > > > RISC-V Foundation governs the official extensions. So not > > > much difference compared how Intel / AMD / ARM governs > > > their ISA extensions. Except you have an option to contribute and influence the process with RISC-V. > > > > Your "Except..." comment makes it sound as if Intel, AMD, and ARM aren't taking ISA input. > > > > They actually do. From what they consider relevant customers. But also from individuals. > > I know Microsoft and some other organizations had a big influence on the definition of AMD64. Do you > know any examples where that happened? Especially interested in contributions done by individuals? > > Ronald
How do you spell avocado?

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