The RISC-V bitmanip ISA extension has conditional moves

By: Gabriele Svelto (gabriele.svelto.delete@this.gmail.com), November 6, 2019 1:21 am
Room: Moderated Discussions
Ronald Maas (ronaldjmaas.delete@this.gmail.com) on November 5, 2019 5:04 pm wrote:
> Now time will tell if extensions are a great idea or a train wreck waiting to happen. My biggest concern
> is if you have 10s of different extensions defined, there are potentially millions of different implementations
> possible that support a slightly different mix of extensions. For Linux all the major distros aligned
> on RV64GC as a baseline which I think is a good thing. I am curious to see how future extensions like
> packed SIMD or vector are going to be handled after they become finalized.

My guess is that embedded vendors will go wild on extensions because it makes sense to have specialized hardware for specialized use-cases, but we won't see that many for general purpose cores. That might hamper general purpose cores in the long run but that's the price to pay if you want binary compatibility and reasonable software complexity.
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Risc-V getting real?Anon2019/10/31 02:10 PM
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        Risc-V getting real?dmcq2019/11/04 05:41 AM
    Documentation QualityKonrad Schwarz2019/11/04 04:43 AM
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        RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas2019/11/02 09:04 AM
          RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/02 02:18 PM
        RISC-V - incompetitive instruction set compared to ARMv8Adrian2019/11/02 09:33 AM
          RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/02 09:49 AM
            RISC-V - incompetitive instruction set compared to ARMv8Wilco2019/11/02 11:20 AM
              RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/02 12:57 PM
              RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas2019/11/03 07:58 AM
                RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/03 09:06 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 05:43 AM
                    RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/04 06:03 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 06:13 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 08:58 AM
                    RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 08:57 AM
                      RISC-V - incompetitive instruction set compared to ARMv8rwessel2019/11/04 09:25 AM
                        RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 09:48 AM
                RISC-V - incompetitive instruction set compared to ARMv8Wilco2019/11/03 11:09 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas2019/11/03 09:44 PM
                    RISC-V - incompetitive instruction set compared to ARMv8Wilco2019/11/04 03:01 PM
                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 03:14 PM
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                RISC-V - incompetitive instruction set compared to ARMv8sylt2019/11/03 12:35 PM
                  RISC-V - incompetitive instruction set compared to ARMv8l2019/11/03 07:26 PM
            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/03 01:25 AM
              The RISC-V bitmanip ISA extension has conditional movesWilco2019/11/03 05:38 AM
                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds2019/11/03 09:03 AM
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 05:29 AM
                  The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 05:38 AM
                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 05:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 05:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 08:36 AM
                            I'm glad you're not that blind :) (NT)none2019/11/04 08:36 AM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 09:23 AM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 05:16 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:42 PM
                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 05:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 05:04 PM
                                  The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 01:21 AM
                                    The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 02:31 AM
                                    The RISC-V bitmanip ISA extension has conditional movesKonrad Schwarz2019/11/06 06:03 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 06:57 AM
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 07:55 AM
                      The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 06:24 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 03:07 PM
                          The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 04:02 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 11:45 PM
                                RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas2019/11/05 04:41 PM
                                  RISC-V - incompetitive instruction set compared to ARMv8anonymou52019/11/05 11:24 PM
                                    The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 11:41 PM
                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 12:12 AM
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 01:22 AM
                                      The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 01:44 AM
                                        The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 01:50 AM
                                        The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 02:08 AM
                                          The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 06:24 AM
                                      The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 04:53 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnoko2019/11/06 10:07 AM
                                        The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 08:35 AM
                              The RISC-V bitmanip ISA extension has conditional movesj2019/11/05 12:43 AM
                          The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/04 04:39 PM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 05:25 PM
                      The RISC-V bitmanip ISA extension has conditional movesAnon2019/11/04 07:31 AM
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                RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 01:45 AM
                  RISC-V - incompetitive instruction set compared to ARMv8none2019/11/04 02:59 AM
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                      RISC-V - incompetitive instruction set compared to ARMv8Adrian2019/11/04 05:10 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 10:03 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/04 10:27 AM
                          RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 11:07 AM
                          RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 12:22 PM
                            RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/04 02:08 PM
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                    Flags RegisterDavid Hess2019/11/05 03:35 PM
                      Flags RegisterWilco2019/11/05 04:54 PM
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      RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 09:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 09:59 AM
          RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 10:11 AM
            RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 10:17 AM
              RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 10:54 AM
                RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/05 06:17 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/05 11:39 AM
                    RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/06 11:19 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Doug S2019/11/06 11:47 AM
                        RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/06 06:36 PM
                          RISC-V - incompetitive instruction set compared to ARMv8Maynard Handley2019/11/06 07:32 PM
                            RISC-V - incompetitive instruction set compared to ARMv8j2019/11/07 03:33 AM
                          RISC-V - incompetitive instruction set compared to ARMv8TREZA2019/11/07 12:31 PM
                            RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/08 07:15 PM
                              RISC-V - incompetitive instruction set compared to ARMv8Maynard Handley2019/11/08 08:40 PM
                                RISC-V - incompetitive instruction set compared to ARMv8none2019/11/09 01:02 AM
                        RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/06 09:36 PM
                          The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/06 11:53 PM
                            Both are excellent ISAs ?Michael S2019/11/07 12:58 AM
                            The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/07 04:33 AM
                              The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 07:31 AM
                            The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/07 08:38 AM
                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 01:32 AM
                            The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 05:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/07 06:50 PM
                                The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 09:47 PM
                                  The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/08 02:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/08 05:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesDavid Hess2019/11/08 07:28 PM
                                      The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/08 08:14 PM
                      RISC-V - incompetitive instruction set compared to ARMv8G. Boniface2019/11/07 05:59 AM
                        Op fusion and superscalar execution do NOT share same hardwareHeikki Kultala2019/11/07 07:39 AM
                          Op fusion and superscalar execution do NOT share same hardwareRonald Maas2019/11/07 08:29 AM
                            Op fusion and superscalar execution do NOT share same hardwareanon2019/11/07 08:37 AM
                            Op fusion and superscalar execution do NOT share same hardwareWilco2019/11/07 11:41 AM
                            Op fusion and superscalar execution do NOT share same hardwareFoo_2019/11/07 11:42 AM
                              Op fusion and superscalar execution do NOT share same hardwareanon.12019/11/07 10:00 PM
                    RISC-V - incompetitive instruction set compared to ARMv8wumpus2019/11/06 04:19 PM
              RISC-V - conditional branches are problematic tooWilco2019/11/04 01:31 PM
                reg-reg branchesMichael S2019/11/06 01:37 AM
                  reg-reg branchesWilco2019/11/07 04:55 PM
      RISC-V - incompetitive instruction set compared to ARMv8Montaray Jack2019/11/08 01:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 06:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 07:12 AM
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