The RISC-V bitmanip ISA extension has conditional moves

By: Adrian (a.delete@this.acm.org), November 6, 2019 2:44 am
Room: Moderated Discussions
Ronald Maas (ronaldjmaas.delete@this.gmail.com) on November 5, 2019 11:41 pm wrote:
> anonymou5 (no.delete@this.spam.com) on November 5, 2019 11:24 pm wrote:
> > > RISC-V Foundation governs the official extensions. So not
> > > much difference compared how Intel / AMD / ARM governs
> > > their ISA extensions. Except you have an option to contribute and influence the process with RISC-V.
> >
> > Your "Except..." comment makes it sound as if Intel, AMD, and ARM aren't taking ISA input.
> >
> > They actually do. From what they consider relevant customers. But also from individuals.
>
> I know Microsoft and some other organizations had a big influence on the definition of AMD64. Do you
> know any examples where that happened? Especially interested in contributions done by individuals?
>
> Ronald


The Larrabee New Instructions, which became AVX-512, i.e. the main advantage that Intel still has over AMD, were mostly defined based on feedback and requests from individuals outside Intel with graphics programming experience, e.g. Michael Abrash.
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                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 07:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 09:36 AM
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                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 06:04 PM
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