The RISC-V bitmanip ISA extension has conditional moves

By: none (none.delete@this.none.com), November 6, 2019 2:08 am
Room: Moderated Discussions
Adrian (a.delete@this.acm.org) on November 6, 2019 1:44 am wrote:
> Ronald Maas (ronaldjmaas.delete@this.gmail.com) on November 5, 2019 11:41 pm wrote:
> > anonymou5 (no.delete@this.spam.com) on November 5, 2019 11:24 pm wrote:
> > > > RISC-V Foundation governs the official extensions. So not
> > > > much difference compared how Intel / AMD / ARM governs
> > > > their ISA extensions. Except you have an option to contribute and influence the process with RISC-V.
> > >
> > > Your "Except..." comment makes it sound as if Intel, AMD, and ARM aren't taking ISA input.
> > >
> > > They actually do. From what they consider relevant customers. But also from individuals.
> >
> > I know Microsoft and some other organizations had a big influence on the definition of AMD64. Do you
> > know any examples where that happened? Especially interested in contributions done by individuals?
> >
> > Ronald
>
>
> The Larrabee New Instructions, which became AVX-512, i.e. the main advantage that Intel
> still has over AMD, were mostly defined based on feedback and requests from individuals
> outside Intel with graphics programming experience, e.g. Michael Abrash.

Wasn't Michael Abrash working for Intel at that time?
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                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds2019/11/03 09:03 AM
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 05:29 AM
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                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 05:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 05:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 08:36 AM
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                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 09:23 AM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 05:16 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:42 PM
                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 05:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 05:04 PM
                                  The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 01:21 AM
                                    The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 02:31 AM
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                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 01:22 AM
                                      The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 01:44 AM
                                        The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 01:50 AM
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                                          The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 06:24 AM
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                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 01:32 AM
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        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 06:03 AM
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