The RISC-V bitmanip ISA extension has conditional moves

By: dmcq (dmcq.delete@this.fano.co.uk), November 6, 2019 5:53 am
Room: Moderated Discussions
Ronald Maas (ronaldjmaas.delete@this.gmail.com) on November 5, 2019 11:41 pm wrote:
> anonymou5 (no.delete@this.spam.com) on November 5, 2019 11:24 pm wrote:
> > > RISC-V Foundation governs the official extensions. So not
> > > much difference compared how Intel / AMD / ARM governs
> > > their ISA extensions. Except you have an option to contribute and influence the process with RISC-V.
> >
> > Your "Except..." comment makes it sound as if Intel, AMD, and ARM aren't taking ISA input.
> >
> > They actually do. From what they consider relevant customers. But also from individuals.
>
> I know Microsoft and some other organizations had a big influence on the definition of AMD64. Do you
> know any examples where that happened? Especially interested in contributions done by individuals?
>
> Ronald

An idea of mine was used in a new instruction which improved the call sequence for a processor That was a while ago! Of course they're interested in anything that would make an appreciable difference. I guess it is getting harder to think of small changes that do that and big ones like scalable vectors take quite a bit of work.
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                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds2019/11/03 10:03 AM
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:29 AM
                  The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:38 AM
                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 07:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 09:36 AM
                            I'm glad you're not that blind :) (NT)none2019/11/04 09:36 AM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:23 AM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 06:16 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 11:42 PM
                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 06:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 06:04 PM
                                  The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 02:21 AM
                                    The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 03:31 AM
                                    The RISC-V bitmanip ISA extension has conditional movesKonrad Schwarz2019/11/06 07:03 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 07:57 AM
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                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 04:07 PM
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                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 02:22 AM
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                                        The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 03:08 AM
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                                      The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 05:53 AM
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                                        The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 09:35 AM
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                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 02:32 AM
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  Risc-V getting real?Konrad Schwarz2019/11/20 08:12 AM
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