Wilco (wilco.dijkstra.delete@this.ntlworld.com) on November 5, 2019 4:54 pm wrote:
> David Hess (davidwhess.delete@this.gmail.com) on November 5, 2019 3:35 pm wrote:
> > Wilco (wilco.dijkstra.delete@this.ntlworld.com) on November 4, 2019 1:49 pm wrote:
> > > David Hess (davidwhess.delete@this.gmail.com) on November 4, 2019 10:05 am wrote:
> > > >
> > > > Maybe you are the person to ask. Why not implement a duplicate
> > > > set of narrow registers to hold all ALU flag
> > > > results? Some ISAs (Power?) implement multiple addressable flag registers but instead, extend this to a
> > > > full set in parallel with the register file removing the need to separately address them on stores.
> > > >
> > > > Not only would store addressing be free since it is just the register address, but
> > > > reads from the parallel register file holding the flags do not compete with regular
> > > > register file reads. For instance if the zero flag was saved even though it can be
> > > > computed at any time, then a test for zero does not require register file access.
> > >
> > > However you'd need 5 extra bits to specify which register produced the flags in any instruction consuming
> > > flags. And that is particularly problematic for branches. Then there is the correctness/security aspect
> > > of code relying on the flags across calls, so you'd need to clear them explicitly.
> > >
> > > Wilco
> >
> > Why would it be a problem for branches? Lacking register operands means they started out
> > shorter anyway. It is not like they would have both a register and flags operand.
>
> You already need 4 bits for the condition code, this adds another 4-5 for the register. That means it's
> impossible to encode conditional branches in a 16-bit instruction (bad for codesize), and it significantly
> reduces branch ranges in a 32-bit instruction (though not as bad as a reg-reg branch format).
Conditional branches are generally to close targets, if not it's an indication of a bad compiler or bad design (in most cases). Even with 6 bit major opcode + 4 bit condition + 5 bit register field one can address between 2^17 and 2^16 instructions.
I don't know why you expect a 16 bit format to have 5 bit register specifiers - an obvious waste - but with support for both 16 and 32 bit conditional branches there's no problem adding two extra bytes wherever there's a need. Most conditionals would still be encodable into the short format.