By: none (none.delete@this.none.com), November 6, 2019 6:57 am
Room: Moderated Discussions
Konrad Schwarz (no.spam.delete@this.no.spam) on November 6, 2019 6:03 am wrote:
> Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on November 6, 2019 1:21 am wrote:
> > My guess is that embedded vendors will go wild on extensions because it makes sense to
> > have specialized hardware for specialized use-cases, but we won't see that many for general
> > purpose cores. That might hamper general purpose cores in the long run but that's the
> > price to pay if you want binary compatibility and reasonable software complexity.
>
> Easy to use instruction extensions was Tensilica's shtick. Now they are part of Cadence.
ARC now part of Synopsys is another such core.
I guess these kinds of cores are more impacted than ARM ones by RISC-V.
> Gabriele Svelto (gabriele.svelto.delete@this.gmail.com) on November 6, 2019 1:21 am wrote:
> > My guess is that embedded vendors will go wild on extensions because it makes sense to
> > have specialized hardware for specialized use-cases, but we won't see that many for general
> > purpose cores. That might hamper general purpose cores in the long run but that's the
> > price to pay if you want binary compatibility and reasonable software complexity.
>
> Easy to use instruction extensions was Tensilica's shtick. Now they are part of Cadence.
ARC now part of Synopsys is another such core.
I guess these kinds of cores are more impacted than ARM ones by RISC-V.
