Real World Technologies - Forums - Thread: Risc-V getting real?

By: David Hess (davidwhess.delete@this.gmail.com), November 6, 2019 7:36 pm

Doug S (foo.delete@this.bar.bar) on November 6, 2019 11:47 am wrote:
> anon.1 (abc.delete@this.def.com) on November 6, 2019 11:19 am wrote:
> >
> > The whole point of RISC was to make
> > decode simple. Now they want to add complexity in decode because, well, the ISA is oversimplified.
>
> The RISC concept was created 40 years ago. Things have changed, designers have a transistor
> budget orders of magnitude larger today so what was appropriate for a decoder in 1980
> shouldn't be a limitation on what is appropriate for a decoder in 2020.

We are back to the situation which produced CISC processors where memory access time, to integrated cache in this case, limits performance so instruction complexity beyond the absolute minimum is not a disadvantage.

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Topic	Posted By	Date
Risc-V getting real?	Anon	2019/10/31 03:10 PM
Risc-V getting real?	Gabriele Svelto	2019/11/01 03:28 AM
Risc-V getting real?	anon	2019/11/02 01:46 AM
Risc-V getting real?	lockederboss	2019/11/02 01:49 AM
Risc-V getting real?	Gabriele Svelto	2019/11/03 02:20 AM
Risc-V getting real?	Michael S	2019/11/03 03:03 AM
Risc-V getting real?	Gabriele Svelto	2019/11/03 04:45 AM
Risc-V getting real?	anon	2019/11/03 08:29 PM
Risc-V getting real?	Gabriele Svelto	2019/11/04 06:39 AM
Risc-V getting real?	dmcq	2019/11/04 06:41 AM
Documentation Quality	Konrad Schwarz	2019/11/04 05:43 AM
Documentation Quality	Gabriele Svelto	2019/11/04 06:31 AM
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RISC-V - incompetitive instruction set compared to ARMv8	Ronald Maas	2019/11/02 10:04 AM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/02 03:18 PM
RISC-V - incompetitive instruction set compared to ARMv8	Adrian	2019/11/02 10:33 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/02 10:49 AM
RISC-V - incompetitive instruction set compared to ARMv8	Wilco	2019/11/02 12:20 PM
RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/02 01:57 PM
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RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/03 10:06 AM
RISC-V - incompetitive instruction set compared to ARMv8	Gabriele Svelto	2019/11/04 06:43 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/04 07:03 AM
RISC-V - incompetitive instruction set compared to ARMv8	Gabriele Svelto	2019/11/04 07:13 AM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 09:58 AM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 09:57 AM
RISC-V - incompetitive instruction set compared to ARMv8	rwessel	2019/11/04 10:25 AM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 10:48 AM
RISC-V - incompetitive instruction set compared to ARMv8	Wilco	2019/11/03 12:09 PM
RISC-V - incompetitive instruction set compared to ARMv8	Ronald Maas	2019/11/03 10:44 PM
RISC-V - incompetitive instruction set compared to ARMv8	Wilco	2019/11/04 04:01 PM
RISC-V - incompetitive instruction set compared to ARMv8	Gabriele Svelto	2019/11/04 04:14 PM
RISC-V - incompetitive instruction set compared to ARMv8	R	2019/11/04 11:35 PM
RISC-V - incompetitive instruction set compared to ARMv8	sylt	2019/11/03 01:35 PM
RISC-V - incompetitive instruction set compared to ARMv8	l	2019/11/03 08:26 PM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/03 02:25 AM
The RISC-V bitmanip ISA extension has conditional moves	Wilco	2019/11/03 06:38 AM
The RISC-V bitmanip ISA extension has conditional moves	Linus Torvalds	2019/11/03 10:03 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 06:29 AM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/04 06:38 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 06:45 AM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/04 06:55 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 07:17 AM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/04 09:36 AM
I'm glad you're not that blind :) (NT)	none	2019/11/04 09:36 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 10:23 AM
The RISC-V bitmanip ISA extension has conditional moves	Maynard Handley	2019/11/04 06:16 PM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 11:42 PM
The RISC-V bitmanip ISA extension has conditional moves	Adrian	2019/11/05 06:25 AM
The RISC-V bitmanip ISA extension has conditional moves	Ronald Maas	2019/11/05 06:04 PM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/06 02:21 AM
The RISC-V bitmanip ISA extension has conditional moves	dmcq	2019/11/06 03:31 AM
The RISC-V bitmanip ISA extension has conditional moves	Konrad Schwarz	2019/11/06 07:03 AM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/06 07:57 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/06 08:55 AM
The RISC-V bitmanip ISA extension has conditional moves	anon	2019/11/04 07:24 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 04:07 PM
The RISC-V bitmanip ISA extension has conditional moves	anon	2019/11/04 05:02 PM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 11:39 PM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/05 12:45 AM
RISC-V - incompetitive instruction set compared to ARMv8	Ronald Maas	2019/11/05 05:41 PM
RISC-V - incompetitive instruction set compared to ARMv8	anonymou5	2019/11/06 12:24 AM
The RISC-V bitmanip ISA extension has conditional moves	Ronald Maas	2019/11/06 12:41 AM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/06 01:12 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/06 02:22 AM
The RISC-V bitmanip ISA extension has conditional moves	Adrian	2019/11/06 02:44 AM
The RISC-V bitmanip ISA extension has conditional moves	Adrian	2019/11/06 02:50 AM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/06 03:08 AM
The RISC-V bitmanip ISA extension has conditional moves	Adrian	2019/11/06 07:24 AM
The RISC-V bitmanip ISA extension has conditional moves	dmcq	2019/11/06 05:53 AM
The RISC-V bitmanip ISA extension has conditional moves	noko	2019/11/06 11:07 AM
The RISC-V bitmanip ISA extension has conditional moves	Ronald Maas	2019/11/07 09:35 AM
The RISC-V bitmanip ISA extension has conditional moves	j	2019/11/05 01:43 AM
The RISC-V bitmanip ISA extension has conditional moves	dmcq	2019/11/04 05:39 PM
The RISC-V bitmanip ISA extension has conditional moves	Maynard Handley	2019/11/04 06:25 PM
The RISC-V bitmanip ISA extension has conditional moves	Anon	2019/11/04 08:31 AM
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RISC-V - incompetitive instruction set compared to ARMv8	dmcq	2019/11/02 03:00 PM
RISC-V - incompetitive instruction set compared to ARMv8	lockederboss	2019/11/03 09:37 AM
RISC-V - incompetitive instruction set compared to ARMv8	j	2019/11/03 03:29 PM
RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/03 10:00 PM
RISC-V - incompetitive instruction set compared to ARMv8	j	2019/11/04 12:30 AM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 02:45 AM
RISC-V - incompetitive instruction set compared to ARMv8	none	2019/11/04 03:59 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/04 05:22 AM
RISC-V - incompetitive instruction set compared to ARMv8	Adrian	2019/11/04 06:10 AM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 11:03 AM
RISC-V - incompetitive instruction set compared to ARMv8	Linus Torvalds	2019/11/04 11:27 AM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 12:07 PM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 01:22 PM
RISC-V - incompetitive instruction set compared to ARMv8	Linus Torvalds	2019/11/04 03:08 PM
Flags Register	David Hess	2019/11/04 11:05 AM
Flags Register	Wilco	2019/11/04 02:49 PM
Flags Register	Maynard Handley	2019/11/04 07:17 PM
Flags Register	David Hess	2019/11/05 04:35 PM
Flags Register	Wilco	2019/11/05 05:54 PM
Flags Register	Megol	2019/11/06 06:11 AM
Flags Register	Maynard Handley	2019/11/07 02:42 PM
RISC-V - instruction fusion	Anon	2019/11/06 06:40 PM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 10:38 AM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 10:59 AM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 11:11 AM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 11:17 AM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 11:54 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon.1	2019/11/05 07:17 AM
RISC-V - incompetitive instruction set compared to ARMv8	Linus Torvalds	2019/11/05 12:39 PM
RISC-V - incompetitive instruction set compared to ARMv8	anon.1	2019/11/06 12:19 PM
RISC-V - incompetitive instruction set compared to ARMv8	Doug S	2019/11/06 12:47 PM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/06 07:36 PM
RISC-V - incompetitive instruction set compared to ARMv8	Maynard Handley	2019/11/06 08:32 PM
RISC-V - incompetitive instruction set compared to ARMv8	j	2019/11/07 04:33 AM
RISC-V - incompetitive instruction set compared to ARMv8	TREZA	2019/11/07 01:31 PM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/08 08:15 PM
RISC-V - incompetitive instruction set compared to ARMv8	Maynard Handley	2019/11/08 09:40 PM
RISC-V - incompetitive instruction set compared to ARMv8	none	2019/11/09 02:02 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon.1	2019/11/06 10:36 PM
The RISC-V bitmanip ISA extension has conditional moves	Ronald Maas	2019/11/07 12:53 AM
Both are excellent ISAs ?	Michael S	2019/11/07 01:58 AM
The RISC-V bitmanip ISA extension has conditional moves	dmcq	2019/11/07 05:33 AM
The RISC-V bitmanip ISA extension has conditional moves	Ronald Maas	2019/11/07 08:31 AM
The RISC-V bitmanip ISA extension has conditional moves	Adrian	2019/11/07 09:38 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/08 02:32 AM
The RISC-V bitmanip ISA extension has conditional moves	anon.1	2019/11/07 06:39 PM
The RISC-V bitmanip ISA extension has conditional moves	Brett	2019/11/07 07:50 PM
The RISC-V bitmanip ISA extension has conditional moves	anon.1	2019/11/07 10:47 PM
The RISC-V bitmanip ISA extension has conditional moves	Brett	2019/11/08 03:00 PM
The RISC-V bitmanip ISA extension has conditional moves	Maynard Handley	2019/11/08 06:00 PM
The RISC-V bitmanip ISA extension has conditional moves	David Hess	2019/11/08 08:28 PM
The RISC-V bitmanip ISA extension has conditional moves	anon.1	2019/11/08 09:14 PM
RISC-V - incompetitive instruction set compared to ARMv8	G. Boniface	2019/11/07 06:59 AM
Op fusion and superscalar execution do NOT share same hardware	Heikki Kultala	2019/11/07 08:39 AM
Op fusion and superscalar execution do NOT share same hardware	Ronald Maas	2019/11/07 09:29 AM
Op fusion and superscalar execution do NOT share same hardware	anon	2019/11/07 09:37 AM
Op fusion and superscalar execution do NOT share same hardware	Wilco	2019/11/07 12:41 PM
Op fusion and superscalar execution do NOT share same hardware	Foo_	2019/11/07 12:42 PM
Op fusion and superscalar execution do NOT share same hardware	anon.1	2019/11/07 11:00 PM
RISC-V - incompetitive instruction set compared to ARMv8	wumpus	2019/11/06 05:19 PM
RISC-V - conditional branches are problematic too	Wilco	2019/11/04 02:31 PM
reg-reg branches	Michael S	2019/11/06 02:37 AM
reg-reg branches	Wilco	2019/11/07 05:55 PM
RISC-V - incompetitive instruction set compared to ARMv8	Montaray Jack	2019/11/08 02:38 AM
RISC-V - incompetitive instruction set compared to ARMv8	Gabriele Svelto	2019/11/08 07:03 AM
Risc-V getting real?	Konrad Schwarz	2019/11/20 08:12 AM

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Body:	No Text David Hess (davidwhess.delete@this.gmail.com) on November 6, 2019 7:36 pm wrote: > Doug S (foo.delete@this.bar.bar) on November 6, 2019 11:47 am wrote: > > anon.1 (abc.delete@this.def.com) on November 6, 2019 11:19 am wrote: > > > > > > The whole point of RISC was to make > > > decode simple. Now they want to add complexity in decode because, well, the ISA is oversimplified. > > > > The RISC concept was created 40 years ago. Things have changed, designers have a transistor > > budget orders of magnitude larger today so what was appropriate for a decoder in 1980 > > shouldn't be a limitation on what is appropriate for a decoder in 2020. > > We are back to the situation which produced CISC processors where memory access time, to integrated cache in > this case, limits performance so instruction complexity beyond the absolute minimum is not a disadvantage. >
How do you spell avocado?

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