By: David Hess (davidwhess.delete@this.gmail.com), November 6, 2019 7:36 pm
Room: Moderated Discussions
Doug S (foo.delete@this.bar.bar) on November 6, 2019 11:47 am wrote:
> anon.1 (abc.delete@this.def.com) on November 6, 2019 11:19 am wrote:
> >
> > The whole point of RISC was to make
> > decode simple. Now they want to add complexity in decode because, well, the ISA is oversimplified.
>
> The RISC concept was created 40 years ago. Things have changed, designers have a transistor
> budget orders of magnitude larger today so what was appropriate for a decoder in 1980
> shouldn't be a limitation on what is appropriate for a decoder in 2020.
We are back to the situation which produced CISC processors where memory access time, to integrated cache in this case, limits performance so instruction complexity beyond the absolute minimum is not a disadvantage.
> anon.1 (abc.delete@this.def.com) on November 6, 2019 11:19 am wrote:
> >
> > The whole point of RISC was to make
> > decode simple. Now they want to add complexity in decode because, well, the ISA is oversimplified.
>
> The RISC concept was created 40 years ago. Things have changed, designers have a transistor
> budget orders of magnitude larger today so what was appropriate for a decoder in 1980
> shouldn't be a limitation on what is appropriate for a decoder in 2020.
We are back to the situation which produced CISC processors where memory access time, to integrated cache in this case, limits performance so instruction complexity beyond the absolute minimum is not a disadvantage.