RISC-V - incompetitive instruction set compared to ARMv8

By: Maynard Handley (name99.delete@this.name99.org), November 6, 2019 8:32 pm
Room: Moderated Discussions
David Hess (davidwhess.delete@this.gmail.com) on November 6, 2019 6:36 pm wrote:
> Doug S (foo.delete@this.bar.bar) on November 6, 2019 11:47 am wrote:
> > anon.1 (abc.delete@this.def.com) on November 6, 2019 11:19 am wrote:
> > >
> > > The whole point of RISC was to make
> > > decode simple. Now they want to add complexity in decode because, well, the ISA is oversimplified.
> >
> > The RISC concept was created 40 years ago. Things have changed, designers have a transistor
> > budget orders of magnitude larger today so what was appropriate for a decoder in 1980
> > shouldn't be a limitation on what is appropriate for a decoder in 2020.
>
> We are back to the situation which produced CISC processors where memory access time, to integrated cache in
> this case, limits performance so instruction complexity beyond the absolute minimum is not a disadvantage.
>

I'd put it slightly differently (and I don't think cache times are even to blame).

Rather the cycle limiting factor on your CPU is probably something like rename or instruction issue. Most logic (certainly basic ALU stuff) is faster than that.
Meaning that any extra functionality value you can throw into a basic ALU operation, without compromising decode and the rest of the system, is basically a freebie.

Hence, for ARM
- various twiddles related to setting and testing flags
- short immediate shifts
- manipulating the value of a CSEL
- addressing modes that are not utterly trivial (allow some adds, allow some shifts)
and some of the standard fusions that are being supported by all the high-end ARM cores.
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                RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/03 10:06 AM
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                    RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/04 07:03 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 07:13 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 09:58 AM
                    RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 09:57 AM
                      RISC-V - incompetitive instruction set compared to ARMv8rwessel2019/11/04 10:25 AM
                        RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 10:48 AM
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                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds2019/11/03 10:03 AM
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:29 AM
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                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 07:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 09:36 AM
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                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:23 AM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 06:16 PM
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                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 06:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 06:04 PM
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                                    The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 03:31 AM
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                      The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 07:24 AM
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                  Flags RegisterWilco2019/11/04 02:49 PM
                    Flags RegisterMaynard Handley2019/11/04 07:17 PM
                    Flags RegisterDavid Hess2019/11/05 04:35 PM
                      Flags RegisterWilco2019/11/05 05:54 PM
                        Flags RegisterMegol2019/11/06 06:11 AM
                          Flags RegisterMaynard Handley2019/11/07 02:42 PM
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      RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 10:38 AM
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            RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 11:17 AM
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                RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/05 07:17 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/05 12:39 PM
                    RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/06 12:19 PM
                      RISC-V - incompetitive instruction set compared to ARMv8Doug S2019/11/06 12:47 PM
                        RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/06 07:36 PM
                          RISC-V - incompetitive instruction set compared to ARMv8Maynard Handley2019/11/06 08:32 PM
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                          RISC-V - incompetitive instruction set compared to ARMv8TREZA2019/11/07 01:31 PM
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                        RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/06 10:36 PM
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                            Both are excellent ISAs ?Michael S2019/11/07 01:58 AM
                            The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/07 05:33 AM
                              The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 08:31 AM
                            The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/07 09:38 AM
                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 02:32 AM
                            The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 06:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/07 07:50 PM
                                The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 10:47 PM
                                  The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/08 03:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/08 06:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesDavid Hess2019/11/08 08:28 PM
                                      The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/08 09:14 PM
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                        Op fusion and superscalar execution do NOT share same hardwareHeikki Kultala2019/11/07 08:39 AM
                          Op fusion and superscalar execution do NOT share same hardwareRonald Maas2019/11/07 09:29 AM
                            Op fusion and superscalar execution do NOT share same hardwareanon2019/11/07 09:37 AM
                            Op fusion and superscalar execution do NOT share same hardwareWilco2019/11/07 12:41 PM
                            Op fusion and superscalar execution do NOT share same hardwareFoo_2019/11/07 12:42 PM
                              Op fusion and superscalar execution do NOT share same hardwareanon.12019/11/07 11:00 PM
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              RISC-V - conditional branches are problematic tooWilco2019/11/04 02:31 PM
                reg-reg branchesMichael S2019/11/06 02:37 AM
                  reg-reg branchesWilco2019/11/07 05:55 PM
      RISC-V - incompetitive instruction set compared to ARMv8Montaray Jack2019/11/08 02:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 07:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 08:12 AM
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