RISC-V - incompetitive instruction set compared to ARMv8

By: anon.1 (abc.delete@this.def.com), November 6, 2019 10:36 pm
Room: Moderated Discussions
Doug S (foo.delete@this.bar.bar) on November 6, 2019 11:47 am wrote:
> anon.1 (abc.delete@this.def.com) on November 6, 2019 11:19 am wrote:
> > The whole point of RISC was to make
> > decode simple. Now they want to add complexity in decode because, well, the ISA is oversimplified.
>
>
> The RISC concept was created 40 years ago. Things have changed, designers have a transistor
> budget orders of magnitude larger today so what was appropriate for a decoder in 1980
> shouldn't be a limitation on what is appropriate for a decoder in 2020.

Pretty damning then that an ISA produced in this decade is based on design principles aimed at solving problems dating back 40 years. Seems like the memo didn’t travel into the academic ivory towers. Also, note that RISC was concerned with pipelining for frequency. They wanted minimum gates in the critical paths. Area is somewhat of a contributor to it but not the main one. ISA decode complexity is. The more encodings you have, the more information you store per instruction and the more work you have to do in decode.
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                        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 09:58 AM
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                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 07:17 AM
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                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 06:04 PM
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                              The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 08:31 AM
                            The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/07 09:38 AM
                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 02:32 AM
                            The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 06:39 PM
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                                The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 10:47 PM
                                  The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/08 03:00 PM
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                            Op fusion and superscalar execution do NOT share same hardwareanon2019/11/07 09:37 AM
                            Op fusion and superscalar execution do NOT share same hardwareWilco2019/11/07 12:41 PM
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                reg-reg branchesMichael S2019/11/06 02:37 AM
                  reg-reg branchesWilco2019/11/07 05:55 PM
      RISC-V - incompetitive instruction set compared to ARMv8Montaray Jack2019/11/08 02:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 07:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 08:12 AM
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