The RISC-V bitmanip ISA extension has conditional moves

By: Ronald Maas (ronaldjmaas.delete@this.gmail.com), November 7, 2019 12:53 am
Room: Moderated Discussions
anon.1 (abc.delete@this.def.com) on November 6, 2019 9:36 pm wrote:
> Doug S (foo.delete@this.bar.bar) on November 6, 2019 11:47 am wrote:
> > anon.1 (abc.delete@this.def.com) on November 6, 2019 11:19 am wrote:
> > > The whole point of RISC was to make
> > > decode simple. Now they want to add complexity in decode because, well, the ISA is oversimplified.
> >
> >
> > The RISC concept was created 40 years ago. Things have changed, designers have a transistor
> > budget orders of magnitude larger today so what was appropriate for a decoder in 1980
> > shouldn't be a limitation on what is appropriate for a decoder in 2020.
>
> Pretty damning then that an ISA produced in this decade is based on design principles aimed at solving problems
> dating back 40 years. Seems like the memo didn’t travel into the academic ivory towers. Also, note that
> RISC was concerned with pipelining for frequency. They wanted minimum gates in the critical paths. Area
> is somewhat of a contributor to it but not the main one. ISA decode complexity is. The more encodings you
> have, the more information you store per instruction and the more work you have to do in decode.

5000 year ago we used wheels for transportation. And today we still use wheels for transportation. Does not necessarily means every old idea is bad.

Once implementation complexity exceeds a certain level and RISC-V implementations start to implement a full spectrum of extensions, caches, branch prediction, etc. the differences between ARMv8 vs RISC-V start to become less relevant from a technology perspective. Performance, energy efficiency, die area, design and validation efforts for processor implementations targeting higher transistor budgets will be closely matched regardless of the ISA.

Because of that, claiming that ARM is superior compared to RISC-V or vice versa, is meaningless. Both are excellent ISAs. It will be the other factors that will drive the implementation choice. Such as licensing terms, maturity of the eco-system, familiarity with certain ISAs, etc. etc.

Ronald
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            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/03 02:25 AM
              The RISC-V bitmanip ISA extension has conditional movesWilco2019/11/03 06:38 AM
                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds2019/11/03 10:03 AM
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:29 AM
                  The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:38 AM
                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 07:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 09:36 AM
                            I'm glad you're not that blind :) (NT)none2019/11/04 09:36 AM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:23 AM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 06:16 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 11:42 PM
                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 06:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 06:04 PM
                                  The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 02:21 AM
                                    The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 03:31 AM
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                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 04:07 PM
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                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 11:39 PM
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                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 02:22 AM
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                          The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/04 05:39 PM
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                          The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 12:53 AM
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                            The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/07 05:33 AM
                              The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 08:31 AM
                            The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/07 09:38 AM
                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 02:32 AM
                            The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 06:39 PM
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        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 07:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 08:12 AM
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