Maynard Handley (name99.delete@this.name99.org) on November 6, 2019 7:32 pm wrote:
> Rather the cycle limiting factor on your CPU is probably something like rename or
> instruction issue. Most logic (certainly basic ALU stuff) is faster than that.
> Meaning that any extra functionality value you can throw into a basic ALU operation,
> without compromising decode and the rest of the system, is basically a freebie.
>
> Hence, for ARM
> - various twiddles related to setting and testing flags
> - short immediate shifts
> - manipulating the value of a CSEL
> - addressing modes that are not utterly trivial (allow some adds, allow some shifts)
> and some of the standard fusions that are being supported by all the high-end ARM cores.

Historically, I'd guess most RISC architectures started with an ISA matching the initial hardware. So if your first Fischer-Price RISC CPU had an adder and shifter as part of the AGU pipeline, then it made sense to have base+index<<shift addressing modes in your ISA. If not, then maybe you just had simpler addressing modes?

But yes, for an architecture designed in the 2010's, it's a bit disappointing RISC-V didn't include them. Oh well.