RISC-V - incompetitive instruction set compared to ARMv8

By: G. Boniface (boniface.delete@this.example.edu), November 7, 2019 6:59 am
Room: Moderated Discussions
anon.1 (abc.delete@this.def.com) on November 6, 2019 11:19 am wrote:
> Seems like the RISC-V
> folks recommend op-fusion, which is another thing I find ridiculous. The whole point of RISC was to make
> decode simple. Now they want to add complexity in decode because, well, the ISA is oversimplified. Take
> that idea further and a uopcache is the next logical step because you can't sustain dispatch bandwidth or
> add extra pipe stages for fusion (it's not magic pixie dust, transistor gates have to be spent). Madness.

Actually, it's not madness. RISC-V is very explicitly architected to allow a wide range of implementations, from "classic RISC" single-issue in-order pipelines to aggressive OoO.

The claim made (which I cannot verify first-hand, but seems plausible) is that once you've spent the transistors on the complex dependency tracking required to implement superscalar execution, then op-fusion comes at minimal incremental cost.

The apparently contradictory claims can both be true because they apply to different points on the cost-performance spectrum. If you want simple decoding and a tight transistor budget, RISC-V (without op fusion) has it. If you want high performance and have a correspondingly lavish transistor budget, RISC-V (with op fusion) has it.

While op fusion requires additional pipeline stages, the claim is that they are the same stages as are required for superscalar execution anyway, so the incremental cost is low.

(On a tangent, I'm reminded of Linus's criticism of weak memory models on the grounds that once you've paid the cost for a high-performance memory subsystem, then stronger memory models come at minimal additional cost. So weaker models burden the programmer with no genuine compensating performance benefit because they only help performance on inherently low-performance implementations.)

< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Risc-V getting real?Anon2019/10/31 03:10 PM
  Risc-V getting real?Gabriele Svelto2019/11/01 03:28 AM
    Risc-V getting real?anon2019/11/02 01:46 AM
      Risc-V getting real?lockederboss2019/11/02 01:49 AM
      Risc-V getting real?Gabriele Svelto2019/11/03 02:20 AM
        Risc-V getting real?Michael S2019/11/03 03:03 AM
          Risc-V getting real?Gabriele Svelto2019/11/03 04:45 AM
        Risc-V getting real?anon2019/11/03 08:29 PM
          Risc-V getting real?Gabriele Svelto2019/11/04 06:39 AM
        Risc-V getting real?dmcq2019/11/04 06:41 AM
    Documentation QualityKonrad Schwarz2019/11/04 05:43 AM
      Documentation QualityGabriele Svelto2019/11/04 06:31 AM
        Documentation QualityAnon2019/11/04 12:28 PM
  Trivium: Andy Glew works for SiFivePaul A. Clayton2019/11/01 10:51 AM
    RISC-V - incompetitive instruction set compared to ARMv8Heikki Kultala2019/11/02 02:31 AM
      RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas2019/11/02 10:02 AM
        RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas2019/11/02 10:04 AM
          RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/02 03:18 PM
        RISC-V - incompetitive instruction set compared to ARMv8Adrian2019/11/02 10:33 AM
          RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/02 10:49 AM
            RISC-V - incompetitive instruction set compared to ARMv8Wilco2019/11/02 12:20 PM
              RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/02 01:57 PM
              RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas2019/11/03 08:58 AM
                RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/03 10:06 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 06:43 AM
                    RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/04 07:03 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 07:13 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 09:58 AM
                    RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 09:57 AM
                      RISC-V - incompetitive instruction set compared to ARMv8rwessel2019/11/04 10:25 AM
                        RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 10:48 AM
                RISC-V - incompetitive instruction set compared to ARMv8Wilco2019/11/03 12:09 PM
                  RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas2019/11/03 10:44 PM
                    RISC-V - incompetitive instruction set compared to ARMv8Wilco2019/11/04 04:01 PM
                      RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/04 04:14 PM
                      RISC-V - incompetitive instruction set compared to ARMv8R2019/11/04 11:35 PM
                RISC-V - incompetitive instruction set compared to ARMv8sylt2019/11/03 01:35 PM
                  RISC-V - incompetitive instruction set compared to ARMv8l2019/11/03 08:26 PM
            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/03 02:25 AM
              The RISC-V bitmanip ISA extension has conditional movesWilco2019/11/03 06:38 AM
                The RISC-V bitmanip ISA extension has conditional movesLinus Torvalds2019/11/03 10:03 AM
                The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:29 AM
                  The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:38 AM
                    The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 06:45 AM
                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 06:55 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 07:17 AM
                          The RISC-V bitmanip ISA extension has conditional movesnone2019/11/04 09:36 AM
                            I'm glad you're not that blind :) (NT)none2019/11/04 09:36 AM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 10:23 AM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 06:16 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 11:42 PM
                              The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/05 06:25 AM
                                The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/05 06:04 PM
                                  The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 02:21 AM
                                    The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 03:31 AM
                                    The RISC-V bitmanip ISA extension has conditional movesKonrad Schwarz2019/11/06 07:03 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 07:57 AM
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 08:55 AM
                      The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 07:24 AM
                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 04:07 PM
                          The RISC-V bitmanip ISA extension has conditional movesanon2019/11/04 05:02 PM
                            The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/04 11:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesnone2019/11/05 12:45 AM
                                RISC-V - incompetitive instruction set compared to ARMv8Ronald Maas2019/11/05 05:41 PM
                                  RISC-V - incompetitive instruction set compared to ARMv8anonymou52019/11/06 12:24 AM
                                    The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/06 12:41 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 01:12 AM
                                        The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/06 02:22 AM
                                      The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 02:44 AM
                                        The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 02:50 AM
                                        The RISC-V bitmanip ISA extension has conditional movesnone2019/11/06 03:08 AM
                                          The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/06 07:24 AM
                                      The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/06 05:53 AM
                                      The RISC-V bitmanip ISA extension has conditional movesnoko2019/11/06 11:07 AM
                                        The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 09:35 AM
                              The RISC-V bitmanip ISA extension has conditional movesj2019/11/05 01:43 AM
                          The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/04 05:39 PM
                          The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/04 06:25 PM
                      The RISC-V bitmanip ISA extension has conditional movesAnon2019/11/04 08:31 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Ronal2019/11/04 08:59 AM
          RISC-V - incompetitive instruction set compared to ARMv8dmcq2019/11/02 03:00 PM
          RISC-V - incompetitive instruction set compared to ARMv8lockederboss2019/11/03 09:37 AM
          RISC-V - incompetitive instruction set compared to ARMv8j2019/11/03 03:29 PM
            RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/03 10:00 PM
              RISC-V - incompetitive instruction set compared to ARMv8j2019/11/04 12:30 AM
                RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 02:45 AM
                  RISC-V - incompetitive instruction set compared to ARMv8none2019/11/04 03:59 AM
                    RISC-V - incompetitive instruction set compared to ARMv8anon2019/11/04 05:22 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Adrian2019/11/04 06:10 AM
                      RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 11:03 AM
                        RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/04 11:27 AM
                          RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 12:07 PM
                          RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 01:22 PM
                            RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/04 03:08 PM
                Flags RegisterDavid Hess2019/11/04 11:05 AM
                  Flags RegisterWilco2019/11/04 02:49 PM
                    Flags RegisterMaynard Handley2019/11/04 07:17 PM
                    Flags RegisterDavid Hess2019/11/05 04:35 PM
                      Flags RegisterWilco2019/11/05 05:54 PM
                        Flags RegisterMegol2019/11/06 06:11 AM
                          Flags RegisterMaynard Handley2019/11/07 02:42 PM
          RISC-V - instruction fusionAnon2019/11/06 06:40 PM
      RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 10:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 10:59 AM
          RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 11:11 AM
            RISC-V - incompetitive instruction set compared to ARMv8Michael S2019/11/04 11:17 AM
              RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/04 11:54 AM
                RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/05 07:17 AM
                  RISC-V - incompetitive instruction set compared to ARMv8Linus Torvalds2019/11/05 12:39 PM
                    RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/06 12:19 PM
                      RISC-V - incompetitive instruction set compared to ARMv8Doug S2019/11/06 12:47 PM
                        RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/06 07:36 PM
                          RISC-V - incompetitive instruction set compared to ARMv8Maynard Handley2019/11/06 08:32 PM
                            RISC-V - incompetitive instruction set compared to ARMv8j2019/11/07 04:33 AM
                          RISC-V - incompetitive instruction set compared to ARMv8TREZA2019/11/07 01:31 PM
                            RISC-V - incompetitive instruction set compared to ARMv8David Hess2019/11/08 08:15 PM
                              RISC-V - incompetitive instruction set compared to ARMv8Maynard Handley2019/11/08 09:40 PM
                                RISC-V - incompetitive instruction set compared to ARMv8none2019/11/09 02:02 AM
                        RISC-V - incompetitive instruction set compared to ARMv8anon.12019/11/06 10:36 PM
                          The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 12:53 AM
                            Both are excellent ISAs ?Michael S2019/11/07 01:58 AM
                            The RISC-V bitmanip ISA extension has conditional movesdmcq2019/11/07 05:33 AM
                              The RISC-V bitmanip ISA extension has conditional movesRonald Maas2019/11/07 08:31 AM
                            The RISC-V bitmanip ISA extension has conditional movesAdrian2019/11/07 09:38 AM
                              The RISC-V bitmanip ISA extension has conditional movesGabriele Svelto2019/11/08 02:32 AM
                            The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 06:39 PM
                              The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/07 07:50 PM
                                The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/07 10:47 PM
                                  The RISC-V bitmanip ISA extension has conditional movesBrett2019/11/08 03:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesMaynard Handley2019/11/08 06:00 PM
                                    The RISC-V bitmanip ISA extension has conditional movesDavid Hess2019/11/08 08:28 PM
                                      The RISC-V bitmanip ISA extension has conditional movesanon.12019/11/08 09:14 PM
                      RISC-V - incompetitive instruction set compared to ARMv8G. Boniface2019/11/07 06:59 AM
                        Op fusion and superscalar execution do NOT share same hardwareHeikki Kultala2019/11/07 08:39 AM
                          Op fusion and superscalar execution do NOT share same hardwareRonald Maas2019/11/07 09:29 AM
                            Op fusion and superscalar execution do NOT share same hardwareanon2019/11/07 09:37 AM
                            Op fusion and superscalar execution do NOT share same hardwareWilco2019/11/07 12:41 PM
                            Op fusion and superscalar execution do NOT share same hardwareFoo_2019/11/07 12:42 PM
                              Op fusion and superscalar execution do NOT share same hardwareanon.12019/11/07 11:00 PM
                    RISC-V - incompetitive instruction set compared to ARMv8wumpus2019/11/06 05:19 PM
              RISC-V - conditional branches are problematic tooWilco2019/11/04 02:31 PM
                reg-reg branchesMichael S2019/11/06 02:37 AM
                  reg-reg branchesWilco2019/11/07 05:55 PM
      RISC-V - incompetitive instruction set compared to ARMv8Montaray Jack2019/11/08 02:38 AM
        RISC-V - incompetitive instruction set compared to ARMv8Gabriele Svelto2019/11/08 07:03 AM
  Risc-V getting real?Konrad Schwarz2019/11/20 08:12 AM
Reply to this Topic
Name:
Email:
Topic:
Body: No Text
How do you spell avocado?