Real World Technologies - Forums - Thread: Risc-V getting real?

By: Ronald Maas (ronaldjmaas.delete@this.gmail.com), November 7, 2019 9:29 am

Heikki Kultala (heikki.kultala.delete@this.tuni.fi) on November 7, 2019 7:39 am wrote:
> Totally bogus claim. The op fusion needs an additional stage in the FRONTEND
> while superscalar execution adds a stage(s) in the backend.
>

On x86 fusion is implemented without requiring any additional pipeline stages. Why are extra pipeline stages suddenly required for fusion on RISC-V?

Ronald

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Topic	Posted By	Date
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Risc-V getting real?	Gabriele Svelto	2019/11/03 02:20 AM
Risc-V getting real?	Michael S	2019/11/03 03:03 AM
Risc-V getting real?	Gabriele Svelto	2019/11/03 04:45 AM
Risc-V getting real?	anon	2019/11/03 08:29 PM
Risc-V getting real?	Gabriele Svelto	2019/11/04 06:39 AM
Risc-V getting real?	dmcq	2019/11/04 06:41 AM
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RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/02 10:49 AM
RISC-V - incompetitive instruction set compared to ARMv8	Wilco	2019/11/02 12:20 PM
RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/02 01:57 PM
RISC-V - incompetitive instruction set compared to ARMv8	Ronald Maas	2019/11/03 08:58 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/03 10:06 AM
RISC-V - incompetitive instruction set compared to ARMv8	Gabriele Svelto	2019/11/04 06:43 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/04 07:03 AM
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RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 09:57 AM
RISC-V - incompetitive instruction set compared to ARMv8	rwessel	2019/11/04 10:25 AM
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RISC-V - incompetitive instruction set compared to ARMv8	Wilco	2019/11/03 12:09 PM
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RISC-V - incompetitive instruction set compared to ARMv8	l	2019/11/03 08:26 PM
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The RISC-V bitmanip ISA extension has conditional moves	Linus Torvalds	2019/11/03 10:03 AM
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The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 06:45 AM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/04 06:55 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 07:17 AM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/04 09:36 AM
I'm glad you're not that blind :) (NT)	none	2019/11/04 09:36 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 10:23 AM
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The RISC-V bitmanip ISA extension has conditional moves	Konrad Schwarz	2019/11/06 07:03 AM
The RISC-V bitmanip ISA extension has conditional moves	none	2019/11/06 07:57 AM
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The RISC-V bitmanip ISA extension has conditional moves	anon	2019/11/04 07:24 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/04 04:07 PM
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The RISC-V bitmanip ISA extension has conditional moves	dmcq	2019/11/06 05:53 AM
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The RISC-V bitmanip ISA extension has conditional moves	Ronald Maas	2019/11/07 09:35 AM
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RISC-V - incompetitive instruction set compared to ARMv8	j	2019/11/03 03:29 PM
RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/03 10:00 PM
RISC-V - incompetitive instruction set compared to ARMv8	j	2019/11/04 12:30 AM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 02:45 AM
RISC-V - incompetitive instruction set compared to ARMv8	none	2019/11/04 03:59 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon	2019/11/04 05:22 AM
RISC-V - incompetitive instruction set compared to ARMv8	Adrian	2019/11/04 06:10 AM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 11:03 AM
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RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 12:07 PM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 01:22 PM
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Flags Register	Wilco	2019/11/04 02:49 PM
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Flags Register	Wilco	2019/11/05 05:54 PM
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RISC-V - instruction fusion	Anon	2019/11/06 06:40 PM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 10:38 AM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 10:59 AM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 11:11 AM
RISC-V - incompetitive instruction set compared to ARMv8	Michael S	2019/11/04 11:17 AM
RISC-V - incompetitive instruction set compared to ARMv8	David Hess	2019/11/04 11:54 AM
RISC-V - incompetitive instruction set compared to ARMv8	anon.1	2019/11/05 07:17 AM
RISC-V - incompetitive instruction set compared to ARMv8	Linus Torvalds	2019/11/05 12:39 PM
RISC-V - incompetitive instruction set compared to ARMv8	anon.1	2019/11/06 12:19 PM
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RISC-V - incompetitive instruction set compared to ARMv8	Maynard Handley	2019/11/06 08:32 PM
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The RISC-V bitmanip ISA extension has conditional moves	Ronald Maas	2019/11/07 12:53 AM
Both are excellent ISAs ?	Michael S	2019/11/07 01:58 AM
The RISC-V bitmanip ISA extension has conditional moves	dmcq	2019/11/07 05:33 AM
The RISC-V bitmanip ISA extension has conditional moves	Ronald Maas	2019/11/07 08:31 AM
The RISC-V bitmanip ISA extension has conditional moves	Adrian	2019/11/07 09:38 AM
The RISC-V bitmanip ISA extension has conditional moves	Gabriele Svelto	2019/11/08 02:32 AM
The RISC-V bitmanip ISA extension has conditional moves	anon.1	2019/11/07 06:39 PM
The RISC-V bitmanip ISA extension has conditional moves	Brett	2019/11/07 07:50 PM
The RISC-V bitmanip ISA extension has conditional moves	anon.1	2019/11/07 10:47 PM
The RISC-V bitmanip ISA extension has conditional moves	Brett	2019/11/08 03:00 PM
The RISC-V bitmanip ISA extension has conditional moves	Maynard Handley	2019/11/08 06:00 PM
The RISC-V bitmanip ISA extension has conditional moves	David Hess	2019/11/08 08:28 PM
The RISC-V bitmanip ISA extension has conditional moves	anon.1	2019/11/08 09:14 PM
RISC-V - incompetitive instruction set compared to ARMv8	G. Boniface	2019/11/07 06:59 AM
Op fusion and superscalar execution do NOT share same hardware	Heikki Kultala	2019/11/07 08:39 AM
Op fusion and superscalar execution do NOT share same hardware	Ronald Maas	2019/11/07 09:29 AM
Op fusion and superscalar execution do NOT share same hardware	anon	2019/11/07 09:37 AM
Op fusion and superscalar execution do NOT share same hardware	Wilco	2019/11/07 12:41 PM
Op fusion and superscalar execution do NOT share same hardware	Foo_	2019/11/07 12:42 PM
Op fusion and superscalar execution do NOT share same hardware	anon.1	2019/11/07 11:00 PM
RISC-V - incompetitive instruction set compared to ARMv8	wumpus	2019/11/06 05:19 PM
RISC-V - conditional branches are problematic too	Wilco	2019/11/04 02:31 PM
reg-reg branches	Michael S	2019/11/06 02:37 AM
reg-reg branches	Wilco	2019/11/07 05:55 PM
RISC-V - incompetitive instruction set compared to ARMv8	Montaray Jack	2019/11/08 02:38 AM
RISC-V - incompetitive instruction set compared to ARMv8	Gabriele Svelto	2019/11/08 07:03 AM
Risc-V getting real?	Konrad Schwarz	2019/11/20 08:12 AM

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Body:	No Text Ronald Maas (ronaldjmaas.delete@this.gmail.com) on November 7, 2019 9:29 am wrote: > Heikki Kultala (heikki.kultala.delete@this.tuni.fi) on November 7, 2019 7:39 am wrote: > > Totally bogus claim. The op fusion needs an additional stage in the FRONTEND > > while superscalar execution adds a stage(s) in the backend. > > > > On x86 fusion is implemented without requiring any additional pipeline stages. > Why are extra pipeline stages suddenly required for fusion on RISC-V? > > Ronald >
How do you spell tangerine? 🍊

Op fusion and superscalar execution do NOT share same hardware

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