The RISC-V bitmanip ISA extension has conditional moves

By: Ronald Maas (ronaldjmaas.delete@this.gmail.com), November 7, 2019 9:35 am
Room: Moderated Discussions
noko (noko.delete@this.noko.com) on November 6, 2019 10:07 am wrote:
> Ronald Maas (ronaldjmaas.delete@this.gmail.com) on November 5, 2019 11:41 pm wrote:
> > anonymou5 (no.delete@this.spam.com) on November 5, 2019 11:24 pm wrote:
> > > > RISC-V Foundation governs the official extensions. So not
> > > > much difference compared how Intel / AMD / ARM governs
> > > > their ISA extensions. Except you have an option to contribute and influence the process with RISC-V.
> > >
> > > Your "Except..." comment makes it sound as if Intel, AMD, and ARM aren't taking ISA input.
> > >
> > > They actually do. From what they consider relevant customers. But also from individuals.
> >
> > I know Microsoft and some other organizations had a big influence on the definition of AMD64. Do you
> > know any examples where that happened? Especially interested in contributions done by individuals?
> >
> > Ronald
>
> I know a decade ago someone from ARM asked several open source contributors about
> enhancement requests for NEON. Looking back at what I requested, addv (saddlv/uaddlv),
> extending vtbl to 128-bits, and vector fdiv all made it into AArch64.
>
> But the latter two were pretty obvious, especially given AArch64
> as a whole, and I'm sure others requested the former too.

Interesting. I was not aware of that.

Ronald
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