By: Adrian (a.delete@this.acm.org), November 7, 2019 9:38 am
Room: Moderated Discussions
Ronald Maas (ronaldjmaas.delete@this.gmail.com) on November 6, 2019 11:53 pm wrote:
>
> 5000 year ago we used wheels for transportation. And today we still use wheels
> for transportation. Does not necessarily means every old idea is bad.
>
> Once implementation complexity exceeds a certain level and RISC-V implementations start to
> implement a full spectrum of extensions, caches, branch prediction, etc. the differences between
There is no problem when a base ISA lacks useful instructions, if there are opcode spaces reserved for extensions.
Nevertheless, an extensible ISA should define all the instruction formats, because otherwise it is certain that the extensions will use inefficiently the instruction code space.
If some addressing modes are missing in the base ISA, it would be OK if the format of the load and store instructions would include reserved fields dedicated for specifying extra addressing modes.
If the base ISA lacks the useful addressing modes and, like RISC-V, it was not designed to be extensible for this feature, then, even if it might be possible to add some extra load/store instructions in some extension, it is certain that the instruction encoding will not be so efficient as when the instruction formats would have been designed from the beginning to include all that might be needed, even if only a small subset would be implemented in the cheap implementations.
So no, targeting cheap implementations is not an excuse for RISC-V. They could have easily designed a decent ISA with only a small subset required to be implemented in small chips.
This is a concept well known since the days of IBM System/360, 55 years ago.
RISC-V has always had only one advantage: ignoring the weird SPARC, it was the only royalty-free ISA for which one had a complete set of tools, i.e. compilers, assembler & linker, so that there was no need to develop those.
Now there are other better alternatives, e.g. MIPS & POWER, but, obviously, for whoever has already adopted RISC-V it makes little sense to switch to yet another ISA, so RISC-V will continue to be used in many embedded applications for an indefinite time.
Unlike for ARM, I do not see any chance for RISC-V to be ever useful in a personal computer, unless it would be a variant so extended that it will have little but the name in common with the initial RISC-V specification.
>
> 5000 year ago we used wheels for transportation. And today we still use wheels
> for transportation. Does not necessarily means every old idea is bad.
>
> Once implementation complexity exceeds a certain level and RISC-V implementations start to
> implement a full spectrum of extensions, caches, branch prediction, etc. the differences between
There is no problem when a base ISA lacks useful instructions, if there are opcode spaces reserved for extensions.
Nevertheless, an extensible ISA should define all the instruction formats, because otherwise it is certain that the extensions will use inefficiently the instruction code space.
If some addressing modes are missing in the base ISA, it would be OK if the format of the load and store instructions would include reserved fields dedicated for specifying extra addressing modes.
If the base ISA lacks the useful addressing modes and, like RISC-V, it was not designed to be extensible for this feature, then, even if it might be possible to add some extra load/store instructions in some extension, it is certain that the instruction encoding will not be so efficient as when the instruction formats would have been designed from the beginning to include all that might be needed, even if only a small subset would be implemented in the cheap implementations.
So no, targeting cheap implementations is not an excuse for RISC-V. They could have easily designed a decent ISA with only a small subset required to be implemented in small chips.
This is a concept well known since the days of IBM System/360, 55 years ago.
RISC-V has always had only one advantage: ignoring the weird SPARC, it was the only royalty-free ISA for which one had a complete set of tools, i.e. compilers, assembler & linker, so that there was no need to develop those.
Now there are other better alternatives, e.g. MIPS & POWER, but, obviously, for whoever has already adopted RISC-V it makes little sense to switch to yet another ISA, so RISC-V will continue to be used in many embedded applications for an indefinite time.
Unlike for ARM, I do not see any chance for RISC-V to be ever useful in a personal computer, unless it would be a variant so extended that it will have little but the name in common with the initial RISC-V specification.
